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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u17739ej3v0an00 (3rd edition) date published september 2008 ns printed in japan application note 78k0/kx2 8-bit single-chip microcontrollers flash memory programming (programmer) ? 78k0/kb2: pd78f0500, 78f0501, 78f0502, 78f0503, 78f0503d, 78f0500a, 78f0501a, 78f0502a, 78f0503a, 78f0503da 78k0/kc2: pd78f0511, 78f0512, 78f0513, 78f0514, 78f0515, 78f0513d, 78f0515d, 78f0511a, 78f0512a, 78f0513a, 78f0514a, 78f0515a, 78f0513da, 78f0515da 78k0/kd2: pd78f0521, 78f0522, 78f0523, 78f0524, 78F0525, 78f0526,78f0527, 78f0527d, 78f0521a, 78f0522a, 78f0523a, 78f0524a, 78f 0525a, 78f0526a, 78f0527a, 78f0527da 78k0/ke2: pd78f0531, 78f0532, 78f0533, 78f0534, 78f0535, 78f0536, 78f0537, 78f0537d, 78f0531a, 78f0532a, 78f0533a, 78f0534a, 78f0535a, 78f0536a, 78f0537a, 78f0537da 78k0/kf2: pd78f0544, 78f0545, 78f0546, 78f0547, 78f0547d, 78f0544a, 78f0545a, 78f0546a, 78f0547a, 78f0547da application note u17739ej3v0an 2 [memo] application note u17739ej3v0an 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 application note u17739ej3v0an 4 the information in this document is current as of may, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": application note u17739ej3v0an 5 introduction target readers this application note is intended for us ers who understand the functions of the 78k0/kx2 and who will use this product to design application systems. purpose the purpose of this applic ation note is to help us ers understand how to develop dedicated flash memory programmers for rewr iting the internal flash memory of the 78k0/kx2. the sample programs and circuit diagrams s hown in this document are for reference only and are not intended for us e in actual design-ins. therefore, these sample programs must be used at the user?s own risk. correct operation is not guarant eed if these sample programs are used. organization this manual consists of the following main sections. ? flash memory programming ? command/data frame format ? description of command processing ? uart communication mode ? 3-wire serial i/o communication mode (csi) ? flash memory programming parameter characteristics how to read this manual it is assumed that the reader of this m anual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ? application note u17739ej3v0an 6 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. device-related documents document name document number 78k0/kb2 user?s manual u17328e 78k0/kc2 user?s manual u17336e 78k0/kd2 user?s manual u17312e 78k0/ke2 user?s manual u17260e 78k0/kf2 user?s manual u17397e 78k/0 series instructions user?s manual u12326e caution the related docum ents listed above are subject to change wit hout notice. be sure to use the latest version of each document when designing. application note u17739ej3v0an 7 contents chapter 1 flash memory programming ................. ...............................................................13 1.1 overview ....................................................................................................................... ...............13 1.2 system configuration........................................................................................................... ......14 1.3 flash memory configuration ......................................... ............................................................ 15 1.4 command list and status list ....................................... ...........................................................1 7 1.4.1 command list ................................................................................................................... ............. 17 1.4.2 status list.................................................................................................................... ................... 18 1.5 power activation and setting flash memory progra mming mode........................................19 1.5.1 mode setting fl owchar t ......................................................................................................... ......... 21 1.5.2 sample progr am ................................................................................................................. ............ 22 1.6 shutting down target power supply............................. ...........................................................23 1.7 command execution flow at flash memory rewriting... .......................................................23 chapter 2 command/data frame format .................. ............................................................26 2.1 command frame transmission processing.................... ........................................................28 2.2 data frame transmission processing ............................. ........................................................28 2.3 data frame reception processing ................................... ........................................................28 chapter 3 description of command processing... ...........................................................29 3.1 status command ................................................................................................................. .......29 3.1.1 descrip tion.................................................................................................................... .................. 29 3.1.2 command frame and st atus frame ................................................................................................. 29 3.2 reset command.................................................................................................................. ........30 3.2.1 descrip tion.................................................................................................................... .................. 30 3.2.2 command frame and st atus frame ................................................................................................. 30 3.3 baud rate set command .......................................................................................................... .31 3.4 oscillating frequency set command ............................... ........................................................31 3.4.1 descrip tion.................................................................................................................... .................. 31 3.4.2 command frame and st atus frame ................................................................................................. 31 3.5 chip erase command............................................................................................................. ....32 3.5.1 descrip tion.................................................................................................................... .................. 32 3.5.2 command frame and st atus frame ................................................................................................. 32 3.6 block erase command............................................................................................................ ...33 3.6.1 descrip tion.................................................................................................................... .................. 33 3.6.2 command frame and st atus frame ................................................................................................. 33 3.7 programming command ............................................................................................................ 34 3.7.1 descrip tion.................................................................................................................... .................. 34 3.7.2 command frame and st atus frame ................................................................................................. 34 3.7.3 data frame and st atus frame .................................................................................................... ...... 34 3.7.4 completion of transferring a ll data and status frame ...................................................................... 35 3.8 verify command ................................................................................................................. ........35 3.8.1 descrip tion.................................................................................................................... .................. 35 3.8.2 command frame and st atus frame ................................................................................................. 35 application note u17739ej3v0an 8 3.8.3 data frame and st atus frame .................................................................................................... ......36 3.9 block blank check command ................................................. ................................................. 37 3.9.1 descrip tion.................................................................................................................... ..................37 3.9.2 command frame and st atus frame................................................................................................. .37 3.10 silicon signature command ..................................................................................................... 3 8 3.10.1 descrip tion.................................................................................................................... ..................38 3.10.2 command frame and st atus frame................................................................................................. .38 3.10.3 silicon signature data frame ................................................................................................... ........38 3.10.4 78k0/kx2 silicon signature list ................................................................................................ ........41 3.11 version get command ............................................................................................................ .. 46 3.11.1 descrip tion.................................................................................................................... ..................46 3.11.2 command frame and st atus frame................................................................................................. .46 3.11.3 version dat a fram e............................................................................................................. .............47 3.12 checksum command ............................................................................................................... .47 3.12.1 descrip tion.................................................................................................................... ..................47 3.12.2 command frame and st atus frame................................................................................................. .47 3.12.3 checksum dat a fram e............................................................................................................ .........48 3.13 security set command........................................................................................................... ... 48 3.13.1 descrip tion.................................................................................................................... ..................48 3.13.2 command frame and st atus frame................................................................................................. .48 3.13.3 data frame and st atus frame .................................................................................................... ......49 3.13.4 internal verify che ck and status frame ......................................................................................... ...49 chapter 4 uart communication mode......................... .......................................................... 51 4.1 command frame transmission processing flowchart..... .................................................... 52 4.2 data frame transmission processing flowchart ........... ....................................................... 53 4.3 data frame reception processing flowchart.................. ....................................................... 54 4.4 reset command .................................................................................................................. ....... 55 4.4.1 processing s equence c hart...................................................................................................... .......55 4.4.2 description of pr ocessing sequenc e ............................................................................................. ..56 4.4.3 status at proce ssing comp letion ................................................................................................ .....56 4.4.4 flowc hart ...................................................................................................................... ..................57 4.4.5 sample progr am ................................................................................................................. ............58 4.5 oscillating frequency set command ................................ ...................................................... 59 4.5.1 processing s equence c hart...................................................................................................... .......59 4.5.2 description of pr ocessing sequenc e ............................................................................................. ..60 4.5.3 status at proce ssing comp letion ................................................................................................ .....60 4.5.4 flowc hart ...................................................................................................................... ..................61 4.5.5 sample progr am ................................................................................................................. ............62 4.6 chip erase command ............................................................................................................. ... 63 4.6.1 processing s equence c hart...................................................................................................... .......63 4.6.2 description of pr ocessing sequenc e ............................................................................................. ..64 4.6.3 status at proce ssing comp letion ................................................................................................ .....64 4.6.4 flowc hart ...................................................................................................................... ..................65 4.6.5 sample progr am ................................................................................................................. ............66 4.7 block erase command ............................................................................................................ .. 67 4.7.1 processing s equence c hart...................................................................................................... .......67 4.7.2 description of pr ocessing sequenc e ............................................................................................. ..68 application note u17739ej3v0an 9 4.7.3 status at proce ssing comp letion................................................................................................ ..... 68 4.7.4 flowc hart ...................................................................................................................... .................. 69 4.7.5 sample progr am ................................................................................................................. ............ 70 4.8 programming command ............................................................................................................ 71 4.8.1 processing s equence c hart ...................................................................................................... ...... 71 4.8.2 description of pr ocessing sequenc e ............................................................................................. .. 72 4.8.3 status at proce ssing comp letion................................................................................................ ..... 73 4.8.4 flowc hart ...................................................................................................................... .................. 74 4.8.5 sample progr am ................................................................................................................. ............ 75 4.9 verify command ................................................................................................................. ........77 4.9.1 processing s equence c hart ...................................................................................................... ...... 77 4.9.2 description of pr ocessing sequenc e ............................................................................................. .. 78 4.9.3 status at proce ssing comp letion................................................................................................ ..... 78 4.9.4 flowc hart ...................................................................................................................... .................. 79 4.9.5 sample progr am ................................................................................................................. ............ 80 4.10 block blank check command............................................. ......................................................82 4.10.1 processing s equence c hart ...................................................................................................... ...... 82 4.10.2 description of pr ocessing sequenc e ............................................................................................. .. 83 4.10.3 status at proce ssing comp letion................................................................................................ ..... 83 4.10.4 flowc hart ...................................................................................................................... .................. 84 4.10.5 sample progr am ................................................................................................................. ............ 85 4.11 silicon signature command ...................................................................................................... 86 4.11.1 processing s equence c hart ...................................................................................................... ...... 86 4.11.2 description of pr ocessing sequenc e ............................................................................................. .. 87 4.11.3 status at proce ssing comp letion................................................................................................ ..... 87 4.11.4 flowc hart ...................................................................................................................... .................. 88 4.11.5 sample progr am ................................................................................................................. ............ 89 4.12 version get command ............................................................................................................ ...90 4.12.1 processing s equence c hart ...................................................................................................... ...... 90 4.12.2 description of pr ocessing sequenc e ............................................................................................. .. 91 4.12.3 status at proce ssing comp letion................................................................................................ ..... 91 4.12.4 flowc hart ...................................................................................................................... .................. 92 4.12.5 sample progr am ................................................................................................................. ............ 93 4.13 checksum command ............................................................................................................... ..94 4.13.1 processing s equence c hart ...................................................................................................... ...... 94 4.13.2 description of pr ocessing sequenc e ............................................................................................. .. 95 4.13.3 status at proce ssing comp letion................................................................................................ ..... 95 4.13.4 flowc hart ...................................................................................................................... .................. 96 4.13.5 sample progr am ................................................................................................................. ............ 97 4.14 security set command........................................................................................................... ....98 4.14.1 processing s equence c hart ...................................................................................................... ...... 98 4.14.2 description of pr ocessing sequenc e ............................................................................................. .. 99 4.14.3 status at proce ssing comp letion................................................................................................ ..... 99 4.14.4 flowc hart ...................................................................................................................... ................ 100 4.14.5 sample progr am ................................................................................................................. .......... 101 application note u17739ej3v0an 10 chapter 5 3-wire serial i/o communication mode (csi) ............................................. 103 5.1 command frame transmission processing flowchart... .................................................... 104 5.2 data frame transmission processing flowchart ........ ........................................................ 105 5.3 data frame reception processing flowchart.................. ..................................................... 106 5.4 status command................................................................................................................. ..... 107 5.4.1 processing s equence c hart...................................................................................................... .....107 5.4.2 description of pr ocessing sequenc e ............................................................................................. 108 5.4.3 status at proce ssing comp letion ................................................................................................ ...108 5.4.4 flowc hart ...................................................................................................................... ................109 5.4.5 sample progr am ................................................................................................................. ..........110 5.5 reset command .................................................................................................................. ..... 112 5.5.1 processing s equence c hart...................................................................................................... .....112 5.5.2 description of pr ocessing sequenc e ............................................................................................. 113 5.5.3 status at proce ssing comp letion ................................................................................................ ...113 5.5.4 flowc hart ...................................................................................................................... ................114 5.5.5 sample progr am ................................................................................................................. ..........115 5.6 oscillating frequency set command ............................... ..................................................... 116 5.6.1 processing s equence c hart...................................................................................................... .....116 5.6.2 description of pr ocessing sequenc e ............................................................................................. 117 5.6.3 status at proce ssing comp letion ................................................................................................ ...117 5.6.4 flowc hart ...................................................................................................................... ................118 5.6.5 sample progr am ................................................................................................................. ..........119 5.7 chip erase command ............................................................................................................. . 120 5.7.1 processing s equence c hart...................................................................................................... .....120 5.7.2 description of pr ocessing sequenc e ............................................................................................. 121 5.7.3 status at proce ssing comp letion ................................................................................................ ...121 5.7.4 flowc hart ...................................................................................................................... ................122 5.7.5 sample progr am ................................................................................................................. ..........123 5.8 block erase command ............................................................................................................ 124 5.8.1 processing s equence c hart...................................................................................................... .....124 5.8.2 description of pr ocessing sequenc e ............................................................................................. 125 5.8.3 status at proce ssing comp letion ................................................................................................ ...125 5.8.4 flowc hart ...................................................................................................................... ................126 5.8.5 sample progr am ................................................................................................................. ..........127 5.9 programming command ......................................................................................................... 128 5.9.1 processing s equence c hart...................................................................................................... .....128 5.9.2 description of pr ocessing sequenc e ............................................................................................. 129 5.9.3 status at proce ssing comp letion ................................................................................................ ...130 5.9.4 flowc hart ...................................................................................................................... ................131 5.9.5 sample progr am ................................................................................................................. ..........132 5.10 verify command................................................................................................................. ...... 134 5.10.1 processing s equence c hart...................................................................................................... .....134 5.10.2 description of pr ocessing sequenc e ............................................................................................. 135 5.10.3 status at proce ssing comp letion ................................................................................................ ...135 5.10.4 flowc hart ...................................................................................................................... ................136 5.10.5 sample progr am ................................................................................................................. ..........137 application note u17739ej3v0an 11 5.11 block blank check command........................................... ......................................................139 5.11.1 processing s equence c hart ...................................................................................................... .... 139 5.11.2 description of pr ocessing sequenc e ............................................................................................. 140 5.11.3 status at proce ssing comp letion................................................................................................ ... 140 5.11.4 flowc hart ...................................................................................................................... ................ 141 5.11.5 sample progr am ................................................................................................................. .......... 142 5.12 silicon signature command ....................................................................................................14 3 5.12.1 processing s equence c hart ...................................................................................................... .... 143 5.12.2 description of pr ocessing sequenc e ............................................................................................. 144 5.12.3 status at proce ssing comp letion................................................................................................ ... 144 5.12.4 flowc hart ...................................................................................................................... ................ 145 5.12.5 sample progr am ................................................................................................................. .......... 146 5.13 version get command ............................................................................................................ .147 5.13.1 processing s equence c hart ...................................................................................................... .... 147 5.13.2 description of pr ocessing sequenc e ............................................................................................. 148 5.13.3 status at proce ssing comp letion................................................................................................ ... 148 5.13.4 flowc hart ...................................................................................................................... ................ 149 5.13.5 sample progr am ................................................................................................................. .......... 150 5.14 checksum command ............................................................................................................... 151 5.14.1 processing s equence c hart ...................................................................................................... .... 151 5.14.2 description of pr ocessing sequenc e ............................................................................................. 152 5.14.3 status at proce ssing comp letion................................................................................................ ... 152 5.14.4 flowc hart ...................................................................................................................... ................ 153 5.14.5 sample progr am ................................................................................................................. .......... 154 5.15 security set command........................................................................................................... ..156 5.15.1 processing s equence c hart ...................................................................................................... .... 156 5.15.2 description of pr ocessing sequenc e ............................................................................................. 157 5.15.3 status at proce ssing comp letion................................................................................................ ... 157 5.15.4 flowc hart ...................................................................................................................... ................ 158 5.15.5 sample progr am ................................................................................................................. .......... 159 chapter 6 flash memory programming parameter characteristics ................161 6.1 flash memory programming parameter characteristics of expanded specification products ( pd78f05xxa) .........................................................................................................161 6.1.1 basic charac terist ics.......................................................................................................... ........... 161 6.1.2 flash memory programmi ng mode setti ng time ............................................................................ 161 6.1.3 programming char acteristics .................................................................................................... .... 162 6.2 flash memory programming parameter char acteristics of conventional-specification products ( pd78f05xx)............................................................................................................164 6.2.1 basic charac terist ics.......................................................................................................... ........... 164 6.2.2 flash memory programmi ng mode setti ng time ............................................................................ 164 6.2.3 programming char acteristics .................................................................................................... .... 165 6.3 simultaneous selection and erasure performe d by block erase command ....................167 6.4 uart communication mode ............................................. ......................................................175 6.5 3-wire serial i/o communication mode........................ ..........................................................178 appendix a circuit diagrams (r eference) ..........................................................................181 application note u17739ej3v0an 12 appendix b revision history ................................................................................................ ..... 189 b.1 major revisions in this edition.............................................................................................. 18 9 b.2 revision history up to previous edition ....................... ........................................................ 190 application note u17739ej3v0an 13 chapter 1 flash memory programming to rewrite the contents of the inte rnal flash memory of the 78k0/kx2, a dedicated flash memory programmer (hereafter referred to as the ?programmer?) is usually used. this application note explains how to develop a dedicated programmer. 1.1 overview the 78k0/kx2 incorporates fi rmware that controls flash memory progra mming. the programming to the internal flash memory is performed by transmitting/receiving co mmands between the programmer and the 78k0/kx2 via serial communication. figure 1-1. system outline of fl ash memory programming in 78k0/kx2 78k0/kx2 serial communication programmer cpu firmware flash memory chapter 1 flash memory programming application note u17739ej3v0an 14 1.2 system configuration examples of the system configurat ion for programming the flash memory are illustrated in figure 1-2. these figures illustrate how to program the flash memory with the programmer, under c ontrol of a host machine. depending on how the programmer is c onnected, the programmer can be us ed in a standalone mode without using the host machine, if a user program has been downloaded to the programmer in advance. for example, nec electronics? flash memory programmer pg-fp5 can execute progra mming either by using the gui software with a host machine c onnected or by itself (standalone). figure 1-2. system configuration examples (1) uart communication mode (lsb-first transfer) programmer flmd0 v dd reset t x d r x d gnd flmd0 v dd reset r x d t x d v ss rs-232c, etc. firmware flash memory device host machine (2) 3-wire serial i/o communication m ode (csi) (msb-first transfer) programmer flmd0 v dd reset sck so si gnd flmd0 v dd reset sck so si v ss rs-232c, etc. firmware flash memory device host machine remark as for the pins used for flash memory pr ogramming and the recommended connections of unused pins, see the user's manual of each product. chapter 1 flash memory programming application note u17739ej3v0an 15 1.3 flash memory configuration the 78k0/kx2 must manage product-spec ific information (such as a device name and memory information). table 1-1 shows the flash memory si ze of the 78k0/kx2 and figure 1-3 show s the configurati on of the flash memory. table 1-1. flash memory size of 78k0/kx2 device name flash memory size pd78f0500, 78f0500a 8 kb pd78f0501, 78f0501a 16 kb pd78f0502, 78f0502a 24 kb 78k0/kb2 pd78f0503, 78f0503a, 78f0503d, 78f0503da 32 kb pd78f0511, 78f0511a 16 kb pd78f0512, 78f0512a 24 kb pd78f0513, 78f0513a, 78f0513d, 78f0513da 32 kb pd78f0514, 78f0514a 48 kb 78k0/kc2 pd78f0515, 78f0515a, 78f0515d, 78f0515da 60 kb pd78f0521, 78f0521a 16 kb pd78f0522, 78f0522a 24 kb pd78f0523, 78f0523a 32 kb pd78f0524, 78f0524a 48 kb pd78F0525, 78F0525a 60 kb pd78f0526, 78f0526a 96 kb 78k0/kd2 pd78f0527, 78f0527a, 78f0527d, 78f0527da 128 kb pd78f0531, 78f0531a 16 kb pd78f0532, 78f0532a 24 kb pd78f0533, 78f0533a 32 kb pd78f0534, 78f0534a 48 kb pd78f0535, 78f0535a 60 kb pd78f0536, 78f0536a 96 kb 78k0/ke2 pd78f0537, 78f0537a, 78f0537d, 78f0537da 128 kb pd78f0544, 78f0544a 48 kb pd78f0545, 78f0545a 60 kb pd78f0546, 78f0546a 96 kb 78k0/kf2 pd78f0547, 78f0547a, 78f0547d, 78f0547da 128 kb chapter 1 flash memory programming application note u17739ej3v0an 16 figure 1-3. flash memory configuration chapter 1 flash memory programming application note u17739ej3v0an 17 1.4 command list and status list the flash memory incorporated in the 78k0/kx2 has functions to manipulate t he flash memory, as listed in table 1- 2. the programmer transmits commands to control these functions to t he 78k0/kx2, and mani pulates the flash memory with checking the response status from the 78k0/kx2. 1.4.1 command list the commands used by the programmer and their functions are listed below. table 1-2. list of commands tran smitted from programmer to 78k0/kx2 command number command name function name function 20h chip erase erases the entire flash memory area. 22h block erase erase erases a specifi ed area in the flash memory. 40h programming write writes data to a s pecified area in the flash memory. 13h verify verify compares the contents in a specified area in the flash memory with data transmitted from the programmer. 32h block blank check blank check checks the erase stat us of a specified block in the flash memory. 70h status acquires the current operating status (status data). c0h silicon signature acquires 78k0/kx2 informat ion (write protocol information). c5h version get acquires version inform ation of the 78k0/kx2 and firmware. b0h checksum information acquisition acquires checksum data of a specified area. a0h security set security se ts security information. 00h reset detects synchronization in communication. 90h oscillating frequency set others specifies the oscillation frequency of the 78k0/kx2. chapter 1 flash memory programming application note u17739ej3v0an 18 1.4.2 status list the following table lists the st atus codes the programmer rece ives from the 78k0/kx2. table 2-7. status code list status code status description 04h command number error error returned if a command not supported is received 05h parameter error error returned if command information (parameter) is invalid 06h normal acknowledgment (ack) normal acknowledgment 07h checksum error error returned if data in a frame transmitted from the programmer is abnormal 0fh verify error error returned if a verify error has occurred upon verifying data transmitted from the programmer 10h protect error error returned if an attempt is made to execute processing that is prohibited by the security set command 15h negative acknowledgment (nack) negative acknowledgment 1ah mrg10 error erase verify error 1bh mrg11 error internal verify error or blank check error during data write 1ch write error write error 20h read error error returned when readi ng of security information failed ffh processing in progress (busy) busy response note note during csi communication, 1-byte ?ffh? may be transmi tted, as well as ?ffh? as the data frame format. reception of a checksum error or nack is treated as an immediate abnormal end in this manual. when a dedicated programmer is developed, how ever, the processing may be retri ed without problem from the wait immediately before transmission of the co mmand that results a checksum error or nack. in this event, limiting the retry count is recommended for preventing infi nite repetition of t he retry operation. although not listed in the above t able, if a time-out error (busy time-out or time-out in data frame reception during uart communication) occurs, it is recommended to s hutdown the power supply to the 78k0/kx2 (refer to 1.6 shutting down target power supply ) and then connect the power supply again. chapter 1 flash memory programming application note u17739ej3v0an 19 1.5 power activation and setting flash memory programming mode to rewrite the contents of the flash memory with the pr ogrammer, the 78k0/kx2 must first be set to the flash memory programming mode by supplying a specific volt age to the flash memory programming mode setting pin (flmd0) in the 78k0/kx2, then releasing a reset. the programmer is received pulse input for rewriting flash memory from flmd0 pin after programming mode transition. the following illustrates a timing chart for setting t he flash memory programming mode and selecting the communication mode. figure 1-4. setting flash memory programmi ng mode and selecting communication mode flmd 0 v dd rese t v dd <1> <2> <3> <4> <5> <1>: power activation (v dd ) <2>: flmd0 = high level <3>: reset release (mode setting) <4>: pulse output starts <5>: pulse output ends the relationship between the setting of the flmd0 pin afte r reset release and the operating mode is shown below. table 1-4. relationship between flmd0 pin setting after reset release and operating mode flmd0 operating mode low (gnd) normal operating mode high (v dd ) flash memory programming mode the following table shows the relationship between the number of flmd0 pulses (pulse counts) and communication modes that can be selected with the 78k0/kx2. table 1-5. relationship between flmd0 pluse counts and communication modes communication mode flmd0 pulse counts port used for communication 0 (when x1 clock (f x ) is used) uart (uart6) 3 (when external main system clock (f exclk ) is used) txd6 (p13), rxd6 (p14) 3-wire serial i/o (csi10) 8 so10 (p12), si10 (p11), sck10 (p10) setting prohibited others ? chapter 1 flash memory programming application note u17739ej3v0an 20 ? uart communication mode the rxd and txd pins are used for uart communicati on. the communication conditions are as shown below. table 1-6. uart communication conditions item description baud rate communication is performed at 9,600 bps until the oscillating frequency set command is transmitted. after the status frame is received, the communication rate is switched to 115,200 bps. after that, the communication rate is fixed to 115,200 bps. parity bit none data length 8 bits (lsb first) stop bit 1 bit the programmer always operates as t he master device during csi communi cation, so the programmer must check whether the processing by the 78k 0/kx2, such as writing or erasing, is normally completed. on the other hand, the status of the master and slave is occasionally exchanged during uart communication, so communication at the optimum timing is possible. caution set the same baud rate to the m aster and slave devices when performing uart communication. ? 3-wire serial i/o communication mode (csi) the sck, so and si pins are used for csi communicati on. the programmer always operates as the master device, so communication may not be performed normally if data is transmitted vi a the sck pin while the 78k0/kx2 is not ready for transmission/reception. the communication data format is msb-first, in 8-bi t units. keep the clock frequency 2.5 mhz or lower. chapter 1 flash memory programming application note u17739ej3v0an 21 1.5.1 mode setting flowchart programming mode setting flmd0 p in low out p ut v dd pin high output (target power supply on) wait start of time measurement until start of reset command processing. uart communication time: t r1 csi communication time: t rc t dp t pr is communication mode uart0 ( flmd0 p ulse = 0 ) ? initialization of serial i/o hardware according to communication mode. uart communication time: t r1 elapsed? csi communication time: t rc elapsed? (t rp +t rpe )/2 refer to table 1-5 for the relationship between the pulse counts and communication modes. yes no output of pulse counts according to communication mode has specified time elapsed until start of reset command p rocessin g ? end yes no next, execute reset command processing for each communication mode. reset p in low out p ut flmd0 p in hi g h out p ut wait reset p in hi g h out p ut wait initialization of serial i/o hardware according to communication mode. chapter 1 flash memory programming application note u17739ej3v0an 22 1.5.2 sample program the following shows a sample program for mode setting processing. /****************************************************************/ /* */ /* connect to flash device */ /* */ /****************************************************************/ void fl_con_dev(void) { extern void init_fl_uart(void); extern void init_fl_csi(void); int n; int pulse; srmk0 = true; uarte0 = false; switch (fl_if){ default: pulse = pulse_uart; break; case flif_uart: pulse = useexclk ? pulse_uart_ex : pulse_uart; break; case flif_csi: pulse = pulse_csi; break; } pfl_res = low; // reset = low pmfl_flmd0 = pm_out; // flmd0 = output mode pfl_flmd0 = low; fl_vdd_hi(); // vdd = high fl_wait(tdp); // wait pfl_flmd0 = hi; // flmd0 = high fl_wait(tpr); // wait pfl_res = hi; // reset = high start_flto(fl_if == flif_csi ? trc : tr1); // start "trc" wait timer fl_wait((trp+trpe)/2); if (fl_if == flif_uart){ init_fl_uart(); // initialize uart h.w.(for flash device control) uarte0 = true; srif0 = false; srmk0 = false; } else{ init_fl_csi(); // initialize csi h.w. } for (n = 0; n < pulse; n++){ // pulse output pfl_flmd0 = low; fl_wait(tpw); chapter 1 flash memory programming application note u17739ej3v0an 23 pfl_flmd0 = hi; fl_wait(tpw); } while(!check_flto()) // timeout trc ? ; // no // start reset command proc. } 1.6 shutting down target power supply after each command execution is complet ed, shut down the power supply to t he target after setting the reset pin to low level, as shown below. set other pins to hi-z when shutting down the power supply to the target. caution shutting down the power supply and inputting a reset during command processing are prohibited. figure 1-5. timing for terminati ng flash memory programming mode reset v dd reset input power shutdown 1.7 command execution flow at flash memory rewriting figure 1-6 illustrates the basic flowchart when flash memory rewriting is perfo rmed with the programmer. other than commands shown in t he figure 1-6, the verify command and checksum command are also be supported. chapter 1 flash memory programming application note u17739ej3v0an 24 figure 1-6. basic flowchart for flash memory rewrite processing basic flow power application to target (see figure 1-4 ) mode setting (reset release) (see 1.5 ) selection of communication mode (pulse input) (see 1.5 ) synchronization processing (reset command) (see 3.2 ) end command execution processing completed? target power shutdown processing (see 1.6 ) reset input and power shutdown during rewriting is prohibited because security information may be lost. no yes uart communication? no yes oscillation frequency setting (oscillation frequency set command) (see 3.4 ) remark figure 1-7 shows executi on example of each command. chapter 1 flash memory programming application note u17739ej3v0an 25 figure 1-7. general command execution flow at flash memory rewriting general command flow end execute programming command (see 3.7 ) execute block erase command (see 3.6 ) block blank check command (see 3.9 ) execute verify command (see 3.8 ) execute security set command (see 3.13 ) yes no the programmer can use the verify command to verify whether data transmission between the programmer and the target device is completed normally. application note u17739ej3v0an 26 chapter 2 command/data frame format the programmer uses the command frame to transmit comm ands to the 78k0/kx2. t he 78k0/kx2 uses the data frame to transmit write data or verify data to the programmer. a header, footer , data length information, and checksum are appended to each frame to enhance the reliability of the transferred data. the following shows the format of a command frame and data frame. figure 2-1. command frame format soh (1 byte) len (1 byte) com (1 byte) command information (variable length) (max. 255 bytes) sum (1 byte) etx (1 byte) figure 2-2. data frame format stx (1 byte) len (1 byte) data (variable length) (max. 256 bytes) sum (1 byte) etx or etb (1 byte) table 2-1. description of symbols in each frame symbol value description soh 01h command frame header stx 02h data frame header len ? data length information (00h indicates 256). command frame: com + command information length data frame: data field length com ? command number sum ? checksum data for a frame obtained by sequentially subtracting all of calculation target data from the initial value (00h) in 1-byte units (borrow is ignored). the calculation targets are as follows. command frame: len + com + all of command information data frame: len + all of data etb 17h footer of data frame other than the last frame etx 03h command frame footer, or footer of last data frame the following shows examples of calculat ing the checksum (sum) for a frame. chapter 2 command/data frame format application note u17739ej3v0an 27 [command frame] no command information is included in the following exam ple of a status command fr ame, so len and com are targets of checksum calculation. soh len com sum etx 01h 01h 70h checksum 03h checksum calculation targets for this command frame, checksum data is obtained as follows. 00h (initial value) ? 01h (len) ? 70h (com) = 8fh (borrow ignored. lower 8 bits only.) the command frame finally transmitted is as follows. soh len com sum etx 01h 01h 70h 8fh 03h [data frame] to transmit a data frame as shown below, len and d1 to d4 are targets of checksum calculation. stx len d1 d2 d3 d4 sum etx 02h 04h ffh 80h 40h 22h checksum 03h checksum calculation targets for this data frame, checksum data is obtained as follows. 00h (initial value) ? 04h (len) ? ffh (d1) ? 80h (d2) ? 40h (d3) ? 22h (d4) = 1bh (borrow ignored. lower 8 bits only.) the data frame finally transmitted is as follows. stx len d1 d2 d3 d4 sum etx 02h 04h ffh 80h 40h 22h 1bh 03h when a data frame is receiv ed, the checksum data is calculated in the same manner, and the obtained value is used to detect a checksum error by judging whether the value is the same as that stor ed in the sum field of the receive data. when a data frame as s hown below is received, for example, a checksum error is detected. stx len d1 d2 d3 d4 sum etx 02h 04h ffh 80h 40h 22h 1ah 03h should be 1bh, if normal chapter 2 command/data frame format application note u17739ej3v0an 28 2.1 command frame transmission processing read the following chapters for details on flowcharts of command processing to transmit command frames, for each communication mode. ? for the uart communication mode, read 4.1 flowchart of command frame transmission processing . ? for the 3-wire serial i/o communication mode (csi), read 5.1 flowchart of command frame transmission processing . 2.2 data frame transmission processing the write data frame (user program), ve rify data frame (user program), and secu rity data frame (security flag) are transmitted as a data frame. read the following chapters for details on flowcharts of command processing to transmit data frames, for each communication mode. ? for the uart communication mode, read 4.2 flowchart of data frame transmission processing . ? for the 3-wire serial i/o communication mode (csi), read 5.2 flowchart of data frame transmission processing . 2.3 data frame reception processing the status frame, silicon signature data frame, versi on data frame, and checksum dat a frame are received as a data frame. read the following chapters for details on flowcharts of command processi ng to receive data frames, for each communication mode. ? for the uart communication mode, read 4.3 flowchart of data frame reception processing . ? for the 3-wire serial i/o communication mode (csi), read 5.3 flowchart of data frame reception processing . application note u17739ej3v0an 29 chapter 3 description of command processing 3.1 status command 3.1.1 description this command is used to check the operation status of the 78k0/kx2 after issuance of each command such as write or erase. after the status command is issued, if the status command frame cannot be received normally in the 78k0/kx2 due to problems based on communication or the like, the status setting will not performed in the 78k0/kx2. as a result, a busy response (ffh), not the status frame, may be rece ived. in such a case, retry the status command. 3.1.2 command frame and status frame figure 3-1 shows the format of a command frame for the status command, and figure 3-2 shows the status frame for the command. figure 3-1. status command fram e (from programmer to 78k0/kx2) soh len com sum etx 01h 01h 70h (status) checksum 03h figure 3-2. status frame for status command (from 78k0/kx2 to programmer) stx len data sum etx 02h n st1 ? stn checksum 03h remarks 1. st1 to stn: status #1 to status #n 2. the length of a status frame varies according to each command (such as write or erase) to be transmitted to the 78k0/kx2. read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? the status command is not used in the uart communication mode. ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.4 status command . caution after each command such as write or erase is transmitted in uart communication, the 78k0/kx2 automatically returns the status frame within a specified time. the status command is therefore not used. if the status command is transmitted in ua rt communication, the co mmand number error is returned. chapter 3 description of command processing application note u17739ej3v0an 30 3.2 reset command 3.2.1 description this command is used to check the establishment of communication between the programmer and the 78k0/kx2 after the communication mode is set. when uart is selected as the mode for communication with the 78k0/kx2, the same b aud rate must be set in the programmer and 78k0/kx2. however, the 78k0/kx2 cannot detect its own baud rate generation clock (f x or f exclk ) frequency so the baud rate cannot be set. it makes det ection of the baud rate generation clock frequency in the 78k0/kx2 possible by sending ?00h? twic e at 9,600 bps from the programmer, meas uring the low-level width of ?00h?, and then calculating the average of two sent signals. the baud rate can consequently be set, which enables synchronous detection in communication. 3.2.2 command frame and status frame figure 3-3 shows the format of a command frame for the reset command, and figure 3-4 shows the status frame for the command. figure 3-3. reset command frame (from programmer to 78k0/kx2) soh len com sum etx 01h 01h 00h (reset) checksum 03h figure 3-4. status frame for reset command (from 78k0/kx2 to programmer) stx len data sum etx 02h 1 st1 checksum 03h remark st1: synchronization detection result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.4 reset command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.5 reset command . chapter 3 description of command processing application note u17739ej3v0an 31 3.3 baud rate set command the 78k0/kx2 does not support the baud rate set command. with the 78k0/kx2, uart communication is perform ed at 9,600 bps until the osc illating frequency set command is transmitted. after the status frame is received, the comm unication rate is switched to 115,200 bps. after that, the communication rate is fixed to 115,200 bps. 3.4 oscillating frequency set command 3.4.1 description this command is used to specify the frequency of f x or f exclk during uart communication. the 78k0/kx2 uses the frequency data in the received packet to realize the baud rate of 115,200 bps. caution with the 78k0/kx2, uart communication is performed at 9,600 bps until the oscillating frequency set command is transmitted. after the status frame is recei ved, the communication rate is swit ched to 115,200 bps. after that, the communication rate is fixed to 115,200 bps. 3.4.2 command frame and status frame figure 3-5 shows the format of a command frame for the oscillating frequency set command, and figure 3-6 shows the status frame for the command. figure 3-5. oscillating frequency set co mmand frame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 05h 90h (oscillating frequency set) d01 d02 d03 d04 checksum 03h remark d01 to d04: oscillation frequency = (d01 0.1 + d02 0.01 + d03 0.001) 10 d04 (unit: khz) settings can be made from 10 khz to 100 mhz, but set the value according to the specifications of each device when actually transmitting the command. d01 to d03 hold unpacked bcds, and d04 holds a signed integer. setting example: to set 6 mhz d01 = 06h d02 = 00h d03 = 00h d04 = 04h oscillation frequency = 6 0.1 10 4 = 6,000 khz = 6 mhz setting example: to set 10 mhz d01 = 01h d02 = 00h d03 = 00h d04 = 05h oscillation frequency = 1 0.1 10 5 = 10,000 khz = 10 mhz chapter 3 description of command processing application note u17739ej3v0an 32 figure 3-6. status frame for oscillating fre quency set command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: oscillation frequency setting result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.5 oscillating frequency set command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.6 oscillating frequency set command . 3.5 chip erase command 3.5.1 description this command is used to erase the entire co ntents of the flash memory. in addition, all of the information that is set by security setting processing can be initialized by chip erase processing, as long as chip erase command execution is impossible due to the security setting (see 3.13 security set command ). 3.5.2 command frame and status frame figure 3-7 shows the format of a command frame for the chip erase command, and figure 3-8 shows the status frame for the command. figure 3-7. chip erase command frame (from programmer to 78k0/kx2) soh len com sum etx 01h 01h 20h (chip erase) checksum 03h figure 3-8. status frame for chip er ase command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: chip erase result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.6 chip erase command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.7 chip erase command . chapter 3 description of command processing application note u17739ej3v0an 33 3.6 block erase command 3.6.1 description specify from the start address of erase start block to the end address of erase end block. it can specify multiple contiguous blocks. however, if block erase command is not impossible by the security setting, the c ontents is not erased (see 3.13 security set command ). 3.6.2 command frame and status frame figure 3-9 shows the format of a command frame for the block erase command, and figure 3-10 shows the status frame for the command. figure 3-9. block erase command frame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 07h 22h (block erase) sah sam sal eah eam eal checksum 03h remark sah, sam, sal: block erase start address (start address of any block) sah: start address, high (bits 23 to 16) (fixed to 00h) sam: start address, middle (bits 15 to 8) (fixed to 00h) sal: start address, low (bits 7 to 0) (fixed to 00h) eah, eam, eal: block erase end address (las t address of the internal flash memory) eah: end address, high (bits 23 to 16) eam: end address, middle (bits 15 to 8) eal: end address, low (bits 7 to 0) figure 3-10. status frame for block erase command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: block erase result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.7 block erase command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.8 block erase command . chapter 3 description of command processing application note u17739ej3v0an 34 3.7 programming command 3.7.1 description this command is used to transmit data by the number of written bytes after the write start address and the write end address are transmitted. this command then writes the user program to the flash memory and verifies it internally. the write start/end address can be set only in the block start/end address units. if both of the status frames (st1 and st2) after the last data transmission indicate ack, the 78k0/kx2 firmware automatically executes internal verify. therefore, the status code validation for th is internal verification is necessary. 3.7.2 command frame and status frame figure 3-11 shows the format of a command frame for the programming command, and figure 3-12 shows the status frame for the command. figure 3-11. programming command fram e (from programmer to 78k0/kx2) soh len com command information sum etx 01h 07h 40h (programming) sah sam sal eah eam eal checksum 03h remark sah, sam, sal: write start addresses eah, eam, eal: write end addresses figure 3-12. status frame for programmi ng command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (a) checksum 03h remark st1 (a): command reception result 3.7.3 data frame and status frame figure 3-13 shows the format of a fram e that includes data to be written, and figure 3-14 shows the status frame for the data. figure 3-13. data frame to be written (from programmer to 78k0/kx2) stx len data sum etx/etb 02h 00h to ffh (00h = 256) write data checksum 03h/17h remark write data: user program to be written figure 3-14. status frame for data frame (from 78k0/kx2 to programmer) stx len data sum etx 02h 02h st1 (b) st2 (b) checksum 03h remark st1 (b): data reception check result st2 (b): write result chapter 3 description of command processing application note u17739ej3v0an 35 3.7.4 completion of transferri ng all data and status frame figure 3-15 shows the status frame after transfer of all data is completed. figure 3-15. status frame after completion of tr ansferring all data (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (c) checksum 03h remark st1 (c): internal verify result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.8 programming command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.9 programming command . 3.8 verify command 3.8.1 description this command is used to compare the data transmitted fr om the programmer with the data read from the 78k0/kx2 (read level) in the specified address range, and check whether they match. the verify start/end address can be set only in the block start/end address units. 3.8.2 command frame and status frame figure 3-16 shows the format of a command frame for the verify command, and figure 3-17 shows the status frame for the command. figure 3-16. verify command frame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 07h 13h (verify) sah sam sal eah eam eal checksum 03h remark sah, sam, sal: verify start addresses eah, eam, eal: verify end addresses figure 3-17. status frame for verify command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (a) checksum 03h remark st1 (a): command reception result chapter 3 description of command processing application note u17739ej3v0an 36 3.8.3 data frame and status frame figure 3-18 shows the format of a fr ame that includes data to be verified, and figure 3-19 shows the status frame for the data. figure 3-18. data frame of data to be verified (from programmer to 78k0/kx2) stx len data sum etx/etb 02h 00h to ffh (00h = 256) verify data checksum 03h/17h remark verify data: user program to be verified figure 3-19. status frame for data frame (from 78k0/kx2 to programmer) stx len data sum etx 02h 02h st1 (b) st2 (b) checksum 03h remark st1 (b): data reception check result st2 (b): verify result note note even if a verify error occurs in the specified address range, ack is always returned as the verify result. the status of all verify errors are reflected in the verify result for the last data. therefore, the occurrence of verify errors can be checked only when all the verify processing for the specified address range is completed. read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.9 verify command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.10 verify command . chapter 3 description of command processing application note u17739ej3v0an 37 3.9 block blank check command 3.9.1 description this command is used to check if a block in the flash memory, with a specified block number, is blank (erased state). specify from the start address of blank check start block to the last address of blank check end block. it can specify multiple contiguous blocks. 3.9.2 command frame and status frame figure 3-20 shows the format of a command frame for the block blank check command, and figure 3-21 shows the status frame for the command. figure 3-20. block blank check comma nd frame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 07h 32h (block blank check) sah sam sal eah eam eal checksum 03h remark sah, sam, sal: block blank check start address (start address of any block) sah: start address, high (bits 23 to 16) sam: start address, middle (bits 15 to 8) sal: start address, low (bits 7 to 0) eah, eam, eal: block blank check end address (last address of any block) eah: end address, high (bits 23 to 16) eam: end address, middle (bits 15 to 8) eal: end address, low (bits 7 to 0) figure 3-21. status frame for block blank check command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: block blank check result read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.10 block blank check command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.11 block blank check command . chapter 3 description of command processing application note u17739ej3v0an 38 3.10 silicon signature command 3.10.1 description this command is used to read the write protocol information (silicon signature) of the device. if the programmer supports a programming protocol that is not supported in the 78k0/kx2, for example, execute this command to select an appropriate protocol in accord ance with the values of the second and third bytes. 3.10.2 command frame and status frame figure 3-22 shows the format of a command frame for t he silicon signature command, and figure 3-23 shows the status frame for the command. figure 3-22. silicon signature command frame (from programmer to 78k0/kx2) soh len com sum etx 01h 01h c0h (silicon signature) checksum 03h figure 3-23. status frame for silicon sign ature command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: command reception result 3.10.3 silicon signature data frame figure 3-24 shows the format of a frame t hat includes silicon signature data. figure 3-24. silicon signature data frame (from 78k0/kx2 to programmer) stx len data sum etx 02h n ven met msc dec end dev scf bot checksum 03h remarks 1. n (len): data length ven: vendor code (nec: 10h) met: macro extension code msc: macro function code dec: device extension code end: internal flash memory last address dev: device name ( pdxx) scf: security flag information bot: boot block number (fixed to 03h) 2. for above fields except boot block number (bot), the lower 7 bits are us ed as data entity, and the highest bit is used as an odd parity. the following shows an example. chapter 3 description of command processing application note u17739ej3v0an 39 table 3-1. example of silicon signature data (in case of pd78f0522 (78k0/kd2)) field contents length (byte) example of silicon signature data note 1 actual value parity ven vendor code (nec) 1 10h (00010000b) 10h added met extension code (fixed in 78k0/kx2) 1 7fh (01111111b) 7fh a dded msc function information (fixed in 78k0/kx2) 1 04h (00000100b) 04h added dec device extension code (fixed in 78k0/kx2) 1 7ch (01111100b) 07h added 7fh (01111111b) bfh (11011111b) end internal flash memory last address (extracted from the lower bytes) 3 01h (00000001b) 005fffh added note 2 c4h (11000100b = ?d?) ?d? 37h (00110111b = ?7?) ?7? 38h (00111000b = ?8?) ?8? 46h (01000110b = ?f?) ?f? b0h (10110000b = ?0?) ?0? b5h (10110101b = ?5?) ?5? 32h (00110010b = ?2?) ?2? 32h (00110010b = ?2?) ?2? 20h (00100000b = ? ?) ? ? dev device name 10 20h (00100000b = ? ?) ? ? added scf security flag information 1 any any added note 3 bot the last block number of the boot block cluster (fixed) 1 03h (00000011b) 03h not added notes 1. 0 and 1 are odd parities (the values to adjust the number of ?1? to be the odd number in a byte) 2. the parity calculation for the e nd field is performed as follows (when the last address is 005fffh) <1> the end field is divided in 7-bit units from the lower digit (the higher 3 bits are discarded). 0 0 5 f f f 00000000 01011111 11111111 000 0000001 0111111 1111111 <2> the odd parity bit is appended to the highest bit. p0000001 p01111111 p111 1111 (p = odd parity bit) = 0000001 10 111111 01111111 = 01 bf 7f <3> the order of the higher, middle, and lower bytes is reversed, as follows. 7f bf 01 chapter 3 description of command processing application note u17739ej3v0an 40 the following shows the procedure to translate the va lues in the end field that has been sent from the microcontroller to the actual address. <1> the order of the higher, middle, and lower bytes is reversed, as follows. 7f bf 01 01 bf 7f <2> checks that the number of ?1? is odd in each byte (this can be performed at another timing). <3> the parity bit is removed and a 3-bit 0 is added to the highest bit. 01 bf 7f 00000001 10111111 01111111 0000001 0111111 1111111 000 0000001 0111111 1111111 <4> the values are translated into groups in 8-bit units. 00000000101111111111111 00000000 01011111 11111111 = 0 0 5 f f f if ?7f bf 01? is given to the end field, t he actual last address is consequently 005fffh. note 3. when security flag information is set using the security set command, the highest bit is fixed to ?1?. if the security flag information is read using the silic on signature command, however, the highest bit is the odd parity. read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.11 silicon signature command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.12 silicon signature command . chapter 3 description of command processing application note u17739ej3v0an 41 3.10.4 78k0/kx2 silicon signature list table 3-2. 78k0/kx2 silicon signature data list item description length (bytes) data (hex) vendor code nec 1 10 extension code extension code 1 7f function code function information 1 04 device information device information 1 7c internal flash memory last address (7-bit data + odd parity bit) 3 3 note 1 device name ( pdxx) 78f0500, 78f0500a, 78f0501, 78f0501a, 78f0502, 78f0502a, 78f0503, 78f0503a, 78f0503d, 78f0503da, 78f0511, 78f0511a, 78f0512, 78f0512a, 78f0513, 78f0513a, 78f0513d, 78f0513da, 78f0514, 78f0514a, 78f0515, 78f0515a, 78f0515d, 78f0515da, 78f0521, 78f0521a, 78f0522, 78f0522a, 78f0523, 78f0523a, 78f0524, 78f0524a, 78F0525, 78F0525a, 78f0526, 78f0526a, 78f0527, 78f0527a, 78f0527d, 78f0527da, 78f0531, 78f0531a, 78f0532, 78f0532a, 78f0533, 78f0533a, 78f0534, 78f0534a, 78f0535, 78f0535a, 78f0536, 78f0536a, 78f0537, 78f0537a, 78f0537d, 78f0537da, 78f0544, 78f0544a, 78f0545, 78f0545a, 78f0546, 78f0546a, 78f0547, 78f0547a, 78f0547d, 78f0547da 10 note 2 security information security information 1 any boot block number the last block number of the boot cluster that is currently selected 1 03 notes 1. list of internal flash memory last addresses item description length (bytes) data (hex) 8 kb (1fffh) 7fbf80 16 kb (3fffh) 7f7f80 24 kb (5fffh) 7fbf01 32 kb (7fffh) 7f7f01 48 kb (bfffh) 7f7f02 60 kb (efffh) 7fdf83 96 kb (17fffh) 7f7f85 internal flash memory last address 128 kb (1ffffh) 3 7f7f07 (notes 2 is listed on the next page.) chapter 3 description of command processing application note u17739ej3v0an 42 notes 2. the device names are listed below. device name list (1/4) nickname device name length (bytes) actual value upper row: signature code lower row: character code c4 37 38 46 b0 b5 b0 b0 20 20 d78f0500 d 7 8 f 0 5 0 0 - - c4 37 38 46 b0 b5 b0 b0 c1 20 d78f0500a d 7 8 f 0 5 0 0 a - c4 37 38 46 b0 b5 b0 31 20 20 d78f0501 d 7 8 f 0 5 0 1 - - c4 37 38 46 b0 b5 b0 31 c1 20 d78f0501a d 7 8 f 0 5 0 1 a - c4 37 38 46 b0 b5 b0 32 20 20 d78f0502 d 7 8 f 0 5 0 2 - - c4 37 38 46 b0 b5 b0 32 c1 20 d78f0502a d 7 8 f 0 5 0 2 a - c4 37 38 46 b0 b5 b0 b3 20 20 d78f0503 d78f0503d d 7 8 f 0 5 0 3 - - c4 37 38 46 b0 b5 b0 b3 c1 20 78k0/kb2 d78f0503a d78f0503da d 7 8 f 0 5 0 3 a - c4 37 38 46 b0 b5 31 31 20 20 d78f0511 d 7 8 f 0 5 1 1 - - c4 37 38 46 b0 b5 31 31 c1 20 d78f0511a d 7 8 f 0 5 1 1 a - c4 37 38 46 b0 b5 31 32 20 20 d78f0512 d 7 8 f 0 5 1 2 - - c4 37 38 46 b0 b5 31 32 c1 20 d78f0512a d 7 8 f 0 5 1 2 a - c4 37 38 46 b0 b5 31 b3 20 20 d78f0513 d78f0513d d 7 8 f 0 5 1 3 - - c4 37 38 46 b0 b5 31 b3 c1 20 d78f0513a d78f0513da d 7 8 f 0 5 1 3 a - c4 37 38 46 b0 b5 31 34 20 20 d78f0514 d 7 8 f 0 5 1 4 - - c4 37 38 46 b0 b5 31 34 c1 20 d78f0514a d 7 8 f 0 5 1 4 a - c4 37 38 46 b0 b5 31 b5 20 20 d78f0515 d78f0515d d 7 8 f 0 5 1 5 - - c4 37 38 46 b0 b5 31 b5 c1 20 78k0/kc2 d78f0515a d78f0515da 10 d 7 8 f 0 5 1 5 a - chapter 3 description of command processing application note u17739ej3v0an 43 device name list (2/4) nickname device name length (bytes) actual value upper row: signature code lower row: character code c4 37 38 46 b0 b5 32 31 20 20 d78f0521 d 7 8 f 0 5 2 1 - - c4 37 38 46 b0 b5 32 31 c1 20 d78f0521a d 7 8 f 0 5 2 1 a - c4 37 38 46 b0 b5 32 32 20 20 d78f0522 d 7 8 f 0 5 2 2 - - c4 37 38 46 b0 b5 32 32 c1 20 d78f0522a d 7 8 f 0 5 2 2 a - c4 37 38 46 b0 b5 32 b3 20 20 d78f0523 d 7 8 f 0 5 2 3 - - c4 37 38 46 b0 b5 32 b3 c1 20 d78f0523a d 7 8 f 0 5 2 3 a - c4 37 38 46 b0 b5 32 34 20 20 d78f0524 d 7 8 f 0 5 2 4 - - c4 37 38 46 b0 b5 32 34 c1 20 d78f0524a d 7 8 f 0 5 2 4 a - c4 37 38 46 b0 b5 32 b5 20 20 d78F0525 d 7 8 f 0 5 2 5 - - c4 37 38 46 b0 b5 32 b5 c1 20 d78F0525a d 7 8 f 0 5 2 5 a - c4 37 38 46 b0 b5 32 b6 20 20 d78f0526 d 7 8 f 0 5 2 6 - - c4 37 38 46 b0 b5 32 b6 c1 20 d78f0526a d 7 8 f 0 5 2 6 a - c4 37 38 46 b0 b5 32 37 20 20 d78f0527 d78f0527d d 7 8 f 0 5 2 7 - - c4 37 38 46 b0 b5 32 37 c1 20 78k0/kd2 d78f0527a d78f0527da 10 d 7 8 f 0 5 2 7 a - chapter 3 description of command processing application note u17739ej3v0an 44 device name list (3/4) nickname device name length (bytes) actual value upper row: signature code lower row: character code c4 37 38 46 b0 b5 b3 31 20 20 d78f0531 d 7 8 f 0 5 3 1 - - c4 37 38 46 b0 b5 b3 31 c1 20 d78f0531a d 7 8 f 0 5 3 1 a - c4 37 38 46 b0 b5 b3 32 20 20 d78f0532 d 7 8 f 0 5 3 2 - - c4 37 38 46 b0 b5 b3 32 c1 20 d78f0532a d 7 8 f 0 5 3 2 a - c4 37 38 46 b0 b5 b3 b3 20 20 d78f0533 d 7 8 f 0 5 3 3 - - c4 37 38 46 b0 b5 b3 b3 c1 20 d78f0533a d 7 8 f 0 5 3 3 a - c4 37 38 46 b0 b5 b3 34 20 20 d78f0534 d 7 8 f 0 5 3 4 - - c4 37 38 46 b0 b5 b3 34 c1 20 d78f0534a d 7 8 f 0 5 3 4 a - c4 37 38 46 b0 b5 b3 b5 20 20 d78f0535 d 7 8 f 0 5 3 5 - - c4 37 38 46 b0 b5 b3 b5 c1 20 d78f0535a d 7 8 f 0 5 3 5 a - c4 37 38 46 b0 b5 b3 b6 20 20 d78f0536 d 7 8 f 0 5 3 6 - - c4 37 38 46 b0 b5 b3 b6 c1 20 d78f0536a d 7 8 f 0 5 3 6 a - c4 37 38 46 b0 b5 b3 37 20 20 d78f0537 d78f0537d d 7 8 f 0 5 3 7 - - c4 37 38 46 b0 b5 b3 37 c1 20 78k0/ke2 d78f0537a d78f0537da 10 d 7 8 f 0 5 3 7 a - chapter 3 description of command processing application note u17739ej3v0an 45 device name list (4/4) nickname device name length (bytes) actual value upper row: signature code lower row: character code c4 37 38 46 b0 b5 34 34 20 20 d78f0544 d 7 8 f 0 5 4 4 - - c4 37 38 46 b0 b5 34 34 c1 20 d78f0544a d 7 8 f 0 5 4 4 a - c4 37 38 46 b0 b5 34 b5 20 20 d78f0545 d 7 8 f 0 5 4 5 - - c4 37 38 46 b0 b5 34 b5 c1 20 d78f0545a d 7 8 f 0 5 4 5 a - c4 37 38 46 b0 b5 34 b6 20 20 d78f0546 d 7 8 f 0 5 4 6 - - c4 37 38 46 b0 b5 34 b6 c1 20 d78f0546a d 7 8 f 0 5 4 6 a - c4 37 38 46 b0 b5 34 37 20 20 d78f0547 d78f0547d d 7 8 f 0 5 4 7 - - c4 37 38 46 b0 b5 34 37 c1 20 78k0/kf2 d78f0547a d78f0547da 10 d 7 8 f 0 5 4 7 a - chapter 3 description of command processing application note u17739ej3v0an 46 3.11 version get command 3.11.1 description this command is used to acquire information on the 78k0/kx2 device version and firmware version. the device version value is fixed to 00h. use this command when the programming parameters must be changed in accordance with the 78k0/kx2 firmware version. caution the firmware version may be updated during firmw are update that does not affect the change of flash programming parameters (at th is time, update of the firmwar e version is not reported). example firmware version and reprogramming parameters 3.11.2 command frame and status frame figure 3-25 shows the format of a command frame for the version get command, and figure 3-26 shows the status frame for the command. figure 3-25. version get command frame (from programmer to 78k0/kx2) soh len com sum etx 01h 01h c5h (version get) checksum 03h figure 3-26. status frame for version get command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: command reception result upgrade that requires changing of flash programming parameters upgrade of items that does not affect the change of flash programming parameters firmware version programming parameters v1.00 parameter a v2.00 parameter b v3.00 chapter 3 description of command processing application note u17739ej3v0an 47 3.11.3 version data frame figure 3-27 shows the data frame of version data. figure 3-27. version data frame (from 78k0/kx2 to programmer) stx len data sum etx 02h 06h dv1 dv2 dv3 fv1 fv2 fv3 checksum 03h remark dv1: integer of device version (fixed to 00h) dv2: first decimal place of device version (fixed to 00h) dv3: second decimal place of device version (fixed to 00h) fv1: integer of firmware version fv2: first decimal place of firmware version fv3: second decimal place of firmware version read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.12 version get command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.13 version get command . 3.12 checksum command 3.12.1 description this command is used to acquire the ch ecksum data in the specified area. for the checksum calculation start/end addr ess, specify a fixed address in bloc k units (1 kb) starting from the top of the flash memory. checksum data is obtained by sequentially subtracting data in the specified address range from the initial value (0000h) in 1-byte units. 3.12.2 command frame and status frame figure 3-28 shows the format of a command frame for the checksum command, and figur e 3-29 shows the status frame for the command. figure 3-28. checksum command frame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 07h b0h (checksum) sah sam sal eah eam eal checksum 03h remark sah, sam, sal: checksum calculation start addresses eah, eam, eal: checksum calculation end addresses figure 3-29. status frame for checksum command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 checksum 03h remark st1: command reception result chapter 3 description of command processing application note u17739ej3v0an 48 3.12.3 checksum data frame figure 3-30 shows the format of a fram e that includes checksum data. figure 3-30. checksum data frame (from 78k0/kx2 to programmer) stx len data sum etx 02h 02h ck1 ck2 checksum 03h remark ck1: higher 8 bits of checksum data ck2: lower 8 bits of checksum data read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.13 checksum command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.14 checksum command . 3.13 security set command 3.13.1 description this command is used to perform security settings (enable or disable of write, block erase, chip erase, and boot block cluster rewriting). by performing these settings wi th this command, rewriting of the flash memory by an unauthorized person can be restricted. caution even after the security setti ng, additional setting of changing from enable to disable can be performed; however, changing from disable to enable is not possible. if an attempt is made to perform such a setting, a protect error (10h) will oc cur. if such setting is required, all of the security flags must first be initialized by executing the chip erase command (the block erase command cannot be used to initialize the security flags). if chip erase or boot block cluster rewrite has been disabled, however, chip erase itself will be impossible, so the settings cannot be erased from the programmer. re-confirmation of security setting execution is therefore recommended before disabling chip erase, due to this programmer specification. 3.13.2 command frame and status frame figure 3-31 shows the format of a command frame for the security set command, and figure 3-32 shows the status frame for the command. the security set command frame includes the block number field and page number field but these fields do not have any particular usage, so set these fields to 00h. figure 3-31. security set command fr ame (from programmer to 78k0/kx2) soh len com command information sum etx 01h 03h a0h (security set) 00h (fixed) 00h (fixed) checksum 03h chapter 3 description of command processing application note u17739ej3v0an 49 figure 3-32. status frame for security set command (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (a) checksum 03h remark st1 (a): command reception result 3.13.3 data frame and status frame figure 3-33 shows the format of a security data frame, and figure 3-34 shows the status frame for the data. figure 3-33. security data fram e (from programmer to 78k0/kx2) stx len data sum etx 02h 02h flg bot checksum 03h remark flg: security flag bot: boot block cluster last block number (fixed to 03h) figure 3-34. status frame for security da ta writing (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (b) checksum 03h remark st1 (b): security data write result 3.13.4 internal verify check and status frame figure 3-35 shows the status frame for internal verify check. figure 3-35. status frame for internal ve rify check (from 78k0/kx2 to programmer) stx len data sum etx 02h 01h st1 (c) checksum 03h remark st1 (c): internal verify result the following table shows the contents in the security flag field. table 3-3. contents of security flag field item contents bit 7 bit 6 bit 5 fixed to ?1? bit 4 boot block cluster rewrite disable flag (1: enab les boot block rewrite, 0: disable boot block rewrite) bit 3 fixed to ?1? bit 2 programming disable flag (1: enable s programming, 0: disable programming) bit 1 block erase disable flag (1: enables block erase, 0: disable block erase) bit 0 chip erase disable flag (1: enables chip erase, 0: disable chip erase) chapter 3 description of command processing application note u17739ej3v0an 50 the following table shows the relationship between the secu rity flag field settings and the enable/disable status of each operation. table 3-4. security flag field and en able/disable status of each operation operating mode flash memory programming mode self-programming mode command operation after security setting : execution possible, : execution impossible u : writing and block erase in boot area are impossible writing and block erase in area other than boot area are possible command security setting item programming chip erase block erase disable programming disable chip erase disable block erase ? all commands can be executed regardless of the security setting values ? only retention of security setting values is possible boot block rewrite disable flag u u same condition as that in flash memory programming mode (on-board/off-board programming) read the following chapters for details on flowcharts of processing sequences between the programmer and the 78k0/kx2, flowcharts of command processing, and sa mple programs for each communication mode. ? for the uart communication mode, read 4.14 security set command . ? for the 3-wire serial i/o co mmunication mo de (csi), read 5.15 security set command . application note u17739ej3v0an 51 chapter 4 uart communication mode each of the symbol (t xx and t wtxx ) shown in the flowchart in this chapter is the symbol of characteristic item in chapter 6 flash memory programming parameter characteristics . for each specified value, refer to chapter 6 flash memory programming parameter characteristics . chapter 4 uart communication mode application note u17739ej3v0an 52 4.1 command frame transmission processing flowchart wait between data transmissions (len ? 1) bytes transmitted? command frame transmission processing t dr (uart) command frame heade r (soh = 01h) transmission wait between data transmissions t dr (uart) data length (len) transmission command number (com) transmission wait between data transmissions t dr (uart) transmits 1-byte command information wait between data transmissions t dr (uart) checksum data (sum) transmission wait between data transmissions t dr (uart) command frame foote r (etx = 03h) transmission end of command frame transmission no yes chapter 4 uart communication mode application note u17739ej3v0an 53 4.2 data frame transmission processing flowchart wait between data transmissions len bytes transmitted? data frame transmission processing t dr (uart) data frame header (stx = 02h) transmission data length (len) transmission wait between data transmissions t dr (uart) transmits 1-byte data wait between data transmissions t dr (uart) checksum data (sum) transmission wait between data transmissions t dr (uart) transmission of last data frame footer (etx = 03h) end of data frame transmission last data frame? transmission of footer other than those of last data frame (etb = 17h) no yes no yes chapter 4 uart communication mode application note u17739ej3v0an 54 4.3 data frame reception processing flowchart t dt data frame reception processing t fd1 /t fd2 data frame header (stx = 02h) received? timed out? reception time-out error data length (len) received? t dt timed out? reception time-out error 1-byte data received? timed out? reception time-out error len bytes received? checksum data (sum) received? t dt timed out? reception time-out error data frame footer received? t dt timed out? reception time-out error checksum error? end of data frame reception checksum error last data frame footer (etx = 03h) or footer other than those of last data frame (etb = 17h) no no yes yes no no yes yes no no no yes yes yes no no yes yes no no yes yes yes no chapter 4 uart communication mode application note u17739ej3v0an 55 4.4 reset command 4.4.1 processing sequence chart programmer 78k0/kx2 reset command processing sequence t com t 12 normal completion [a] wait from previous frame reception until next command transmission <1> <3> <2> low level output (00h @ 9,600 bps) <4> low level output (00h @ 9,600 bps) <6> reset command frame transmission t 2c <5> wait reception status [ack/other than ack] ack time-out error [c] retry count over? note [yes/no] other than ack abnormal termination [b] yes no go to <5> <8> status frame reception wait t wt0 time-out check for status frame reception <7> time-out occurs status frame received within specified time note do not exceed the retry count for the reset command transmission (up to 16 times). chapter 4 uart communication mode application note u17739ej3v0an 56 4.4.2 description of processing sequence <1> waits from the previous frame reception unt il the next command processing starts (wait time t com ). <2> the low level is output (data 00h is transmitted at 9,600 bps). <3> wait state (wait time t 12 ). <4> the low level is output (data 00h is transmitted at 9,600 bps). <5> wait state (wait time t 2c ). <6> the reset command is transmitted by command frame transmission processing. <7> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt0 ). <8> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: the retry count ( t rs ) is checked. the sequence is re-executed from <5 > if the retry count is not over. if the retry count is over, the processing ends abnormally [b]. 4.4.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and synchronization between the programmer and the 78k0/kx2 has been established. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. chapter 4 uart communication mode application note u17739ej3v0an 57 4.4.4 flowchart t wt0 (uart) wait from previous frame reception until next command transmission wait command frame transmission processing (reset) status = ack? retry count over? normal completion [a] abnormal termination [b] reset command processing t com t 12 transmits ?00? at 9,600 bps transmits ?00? at 9,600 bps wait t 2c status frame received? timed out? time-out error [c] no no no no yes yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 58 4.4.5 sample program the following shows a sample program for reset command processing. /****************************************************************/ /* */ /* reset command */ /* */ /****************************************************************/ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_reset(void) { u16 rc; u32 retry; set_uart0_br(br_9600); // change to 9600bps fl_wait(tcom); // wait putc_ua(0x00); // send 0x00 @ 9600bps fl_wait(t12); // wait putc_ua(0x00); // send 0x00 @ 9600bps for (retry = 0; retry < trs; retry++){ fl_wait(t2c); // wait put_cmd_ua(fl_com_reset, 1, fl_cmd_prm); // send reset command rc = get_sfrm_ua(fl_ua_sfrm, twt0_to); if (rc == flc_dfto_err) // t.o. ? break; // yes // case [c] if (rc == flc_ack){ // ack ? break; // yes // case [a] } else{ nop(); } //continue; // case [b] (if exit from loop) } // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 59 4.5 oscillating frequency set command 4.5.1 processing sequence chart programmer 78k0/kx2 oscillating frequency set command processing sequence t com normal completion [a] <1> wait from previous frame reception until next command transmission <2> oscillating frequency set command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <5> status frame reception t wt9 time-out check fo r status frame reception time-out occurs status frame received within specified time <4> <3> switching uart communication baud rate to 115,200 bps. chapter 4 uart communication mode application note u17739ej3v0an 60 4.5.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the oscillating frequency set command is transmi tted by command frame transmission processing. <3> after the status frame is receiv ed, the uart communication rate is s witched to 115,200 bps. after that, the communication rate is fixed to 115,200 bps <4> a time-out check is performed from command transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt9 ). <5> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [b] 4.5.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the operating frequency was correctly set to the 78k0/kx2. parameter error 05h the oscillation frequency value is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. chapter 4 uart communication mode application note u17739ej3v0an 61 4.5.4 flowchart wait from previous frame reception until next command transmission status = ack? oscillating frequency set command processing t com command frame transmission processing (oscillating frequency set) normal completion [a] status frame received? timed out? time-out error [c] t wt9 abnormal termination [b] yes yes yes no no no uart communication is performed at 9,600 bps until the oscillating frequency set command is transmitted. after the status frame is received, the communication rate is switched to 115,200 bps. after that, the communication rate is fixed to 115,200 bps. switches uart communication baud rate to 115,200 bps. chapter 4 uart communication mode application note u17739ej3v0an 62 4.5.5 sample program the following shows a sample program for oscillating frequency set command processing. /****************************************************************/ /* */ /* set flash device clock value command */ /* */ /****************************************************************/ /* [i] u8 clk[4] ... frequency data(d1-d4) */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_setclk(u8 clk[]) { u16 rc; fl_cmd_prm[0] = clk[0]; // "d01" fl_cmd_prm[1] = clk[1]; // "d02" fl_cmd_prm[2] = clk[2]; // "d03" fl_cmd_prm[3] = clk[3]; // "d04" fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_set_osc_freq, 5, fl_cmd_prm); set_flbaud(br_115200); // change baud-rate set_uart0_br(br_115200); // change baud-rate (h.w.) rc = get_sfrm_ua(fl_ua_sfrm, twt9_to); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 63 4.6 chip erase command 4.6.1 processing sequence chart programmer 78k0/kx2 chip erase command processing sequence normal completion [a] <1> wait from previous frame reception until next command transmission <2> chip erase command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <4> status frame reception t com time-out check for status frame reception <3> t wt1 status frame received within specified time time-out occurs chapter 4 uart communication mode application note u17739ej3v0an 64 4.6.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the chip erase command is transmitted by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt1 ). <4> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [b] 4.6.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and chip erase was performed normally. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h chip erase is pr ohibited by the security setting. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] erase error 1ah an erase error has occurred. time-out error [c] ? the status frame was not received within the specified time. chapter 4 uart communication mode application note u17739ej3v0an 65 4.6.4 flowchart waits from previous frame reception until next command transmission status = ack? chip erase command processing t com command frame transmission processing (chip erase) normal completion [a] t wt1 status frame received? timed out? time-out error [c] abnormal termination [b] no no no yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 66 4.6.5 sample program the following shows a sample program for chip erase command processing. /****************************************************************/ /* */ /* erase all(chip) command */ /* */ /****************************************************************/ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_erase_all(void) { u16 rc; fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_erase_chip, 1, fl_cmd_prm); // send erase chip command rc = get_sfrm_ua(fl_ua_sfrm, twt1_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 67 4.7 block erase command 4.7.1 processing sequence chart programmer 78k0/kx2 block erase command processing sequence t com <1> wait from previous frame reception until next command transmission <2> block erase command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <4> status frame reception normal completion [a] time-out check for status frame reception <3> t wt2 time-out occurs status frame received within specified time chapter 4 uart communication mode application note u17739ej3v0an 68 4.7.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the block erase command is transmitted by command frame transmission processing. <3> a time-out check is performed from command transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt2 ). <4> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [b] 4.7.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and block erase was performed normally. parameter error 05h the number of blocks is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h write, block erase, or chip erase is prohibited by the security setting. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] erase error 1ah an erase error has occurred. time-out error [c] ? the status frame was not received within the specified time. chapter 4 uart communication mode application note u17739ej3v0an 69 4.7.4 flowchart wait from previous frame reception until next command transmission status = ack? block erase command processing t com command frame transmission processing (block erase) normal completion [a] t wt2 status frame received? timed out? time-out error [c] abnormal termination [b] yes yes yes no no no chapter 4 uart communication mode application note u17739ej3v0an 70 4.7.5 sample program the following shows a sample program for block erase command processing for one block. /****************************************************************/ /* */ /* erase block command */ /* */ /****************************************************************/ /* [i] u16 sblk ... start block to erase (0...255) */ /* [i] u16 eblk ... end block to erase (0...255) */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_erase_blk(u16 sblk, u16 eblk) { u16 rc; u32 wt2_max; u32 top, bottom; top = get_top_addr(sblk); // get start address of start block bottom = get_bottom_addr(eblk); // get end address of end block set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal wt2_max = make_wt2_max(sblk, eblk); fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_erase_block, 7, fl_cmd_prm); // send erase chip command rc = get_sfrm_ua(fl_ua_sfrm, wt2_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 71 4.8 programming command 4.8.1 processing sequence chart programmer 78k0/kx2 programming command processing sequence t com t wt3 reception status [ack/other than ack] <4> status frame reception ack <1> wait from previous frame reception until next command transmission <3> time-out check for status frame reception <2> programming command frame transmission abnormal termination [b] other than ack normal completion [a] t fd3 (uart) <5> wait from previous frame reception until next data frame transmission data frame (user data) transmission t wt4 <7> time- out check for status frame reception <8> status frame reception reception status (st1) [ack/other than ack] abnormal termination [b] other than ack reception status (st2) [ack/other than ack] ack abnormal termination [d] all data frames transmitted? [yes/no] ack go to <5> no <9> time-out check for status frame reception t wt5 number of blocks yes <10> status frame reception reception status [ack/other than ack] abnormal termination [e] other than ack ack time-out occurs status frame received within specified time time-out error [c] time-out occurs status frame received within specified time time-out error [c] time-out occurs status frame received within specified time other than ack time-out error [c] <6> chapter 4 uart communication mode application note u17739ej3v0an 72 4.8.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the programming command is transmitted by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt3 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> waits from the previous frame reception until the next data frame transmission (wait time t fd3 (uart) ). <6> user data is transmitted by data frame transmission processing. <7> a time-out check is performed from user data transmission until dat a frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt4 ). <8> the status code (st1/st2) is checked (also re fer to the processing sequence chart and flowchart). when st1 ack: abnormal termination [b] when st1 = ack: the following processing is performed according to the st2 value. ? when st2 = ack: proceeds to <9> when trans mission of all data frames is completed. if there still remain data frames to be tr ansmitted, the processing re-executes the sequence from <5>. ? when st2 ack: abnormal termination [d] <9> a time-out check is perform ed until status fr ame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt5 number of blocks). <10> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [e] chapter 4 uart communication mode application note u17739ej3v0an 73 4.8.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed nor mally and the user data was written normally. parameter error 05h the specified start/ end address is out of the flash memory range, or is not a multiple of 8. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h write is prohi bited by the security setting. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. abnormal termination [d] write error 1ch (st2) a write error has occurred. abnormal termination [e] mrg11 error 1bh an internal verify error has occurred. chapter 4 uart communication mode application note u17739ej3v0an 74 4.8.4 flowchart wait from previous frame reception until next command transmission status = ack? programming command processing t com t wt3 command frame transmission processing (programming) normal completion [a] wait from previous frame reception until next command transmission t fd3 (uart) data frame transmission processing (user program) st1 = ack? abnormal termination [b] st2 = ack? abnormal termination [d] all data frame s transmitted? status = ack? abnormal termination [e] status frame received? timed out? time-out error [c] t wt4 status frame received? timed out? time-out error [c] t wt5 number of blocks status frame received? timed out? time-out error [c] abnormal termination [b] no no yes no no no no no no no no no yes yes yes yes yes yes yes yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 75 4.8.5 sample program the following shows a sample program for programming command processing. /****************************************************************/ /* */ /* write command */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ #define fl_st2_ua (fl_ua_sfrm[ofs_sta_pld+1]) u16 fl_ua_write(u32 top, u32 bottom) { u16 rc; u32 send_head, send_size; bool is_end; u16 block_num; /************************************************/ /* set params */ /************************************************/ set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal block_num = get_block_num(top, bottom); // get block num /************************************************/ /* send command & check status */ /************************************************/ fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_write, 7, fl_cmd_prm); // send "programming" command rc = get_sfrm_ua(fl_ua_sfrm, twt3_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send user data */ /************************************************/ send_head = top; chapter 4 uart communication mode application note u17739ej3v0an 76 while(1){ // make send data frame if ((bottom - send_head) > 256){ // rest size > 256 ? is_end = false; // yes, not is_end frame send_size = 256; // transmit size = 256 byte } else{ is_end = true; send_size = bottom - send_head + 1; // transmit size = (bottom ? // send_head)+1 byte } memcpy(fl_txdata_frm, rom_buf+send_head, send_size); // set data frame // payload send_head += send_size; fl_wait(tfd3_ua); // wait before sending data frame put_dfrm_ua(send_size, fl_txdata_frm, is_end); // send user data rc = get_sfrm_ua(fl_ua_sfrm, twt4_max); // get status frame switch(rc) { case flc_no_err: break; // continue case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } if (fl_st2_ua != flst_ack){ // st2 = ack ? rc = decode_status(fl_st2_ua); // no return rc; // case [d] } if (is_end) break; } /************************************************/ /* check internally verify */ /************************************************/ rc = get_sfrm_ua(fl_ua_sfrm, (twt5_max * block_num)); // get status frame again // switch(rc) { // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [e] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 77 4.9 verify command 4.9.1 processing sequence chart programmer 78k0/kx2 verify command processing sequence t com t wt6 reception status [ack/other than ack] <4> status frame reception ack <1> wait from previous frame reception until next command transmission <3> time-out check for status frame reception <2> verify command frame transmission abnormal termination [b] other than ack normal completion [a] t fd3 (uart) <5> wait from previous frame reception until next data frame transmission <6> data frame (user data for verify) transmission t wt7 <7> time-out check for status frame reception <8> status frame reception (st1/st2) reception status (st1) [ack/other than ack] abnormal termination [b] other than ack reception status (st2) [ack/other than ack] ack abnormal termination [d] other than ack ack all data frames transmitted? [yes/no] go to <5> no yes time-out occurs status frame received within specified time time-out error [c] time-out occurs status frame received within specified time time-out error [c] chapter 4 uart communication mode application note u17739ej3v0an 78 4.9.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the verify command is transmitted by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt6 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> waits from the previous frame reception until the next data frame transmission (wait time t fd3 (uart) ). <6> user data for verifying is transmitt ed by data frame transmission processing. <7> a time-out check is performed from user data transmission until stat us frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt7 ). <8> the status code (st1/st2) is checked (also re fer to the processing sequence chart and flowchart). when st1 ack: abnormal termination [b] when st1 = ack: the following processing is performed according to the st2 value. ? when st2 = ack: if transmission of all data frames is completed, the processing ends normally [a]. if there still remain data frames to be tr ansmitted, the processing re-executes the sequence from <5>. ? when st2 ack: abnormal termination [d] 4.9.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the verify was completed normally. parameter error 05h the specified start/ end address is out of the flash memory range. checksum error 07h the checksum of the transmitted command frame or data frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. abnormal termination [d] verify error 0fh (st2) the verify has failed, or another error has occurred. chapter 4 uart communication mode application note u17739ej3v0an 79 4.9.4 flowchart wait from previous frame reception until next command transmission st1 = ack? verify command processing t com t wt6 command frame transmission processing (verify) normal completion [a] wait from previous frame reception until next data frame transmission t fd3 (uart) data frame transmission processing (user program) st1 = ack? st2 = ack? all data frames transmitted? status frame received? timed out? time-out error [c] t wt7 status frame received? timed out? time-out error [c] abnormal termination [b] abnormal termination [b] abnormal termination [d] no no no no no no no no yes yes yes yes yes yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 80 4.9.5 sample program the following shows a sample program for verify command processing. /****************************************************************/ /* */ /* verify command */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_verify(u32 top, u32 bottom) { u16 rc; u32 send_head, send_size; bool is_end; /************************************************/ /* set params */ /************************************************/ set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal /************************************************/ /* send command & check status */ /************************************************/ fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_verify, 7, fl_cmd_prm); // send verify command rc = get_sfrm_ua(fl_ua_sfrm, twt6_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send user data */ /************************************************/ send_head = top; while(1){ // make send data frame if ((bottom - send_head) > 256){ // rest size > 256 ? chapter 4 uart communication mode application note u17739ej3v0an 81 is_end = false; // yes, not is_end frame send_size = 256; // transmit size = 256 byte } else{ is_end = true; send_size = bottom - send_head + 1; // transmit size = (bottom // - send_head)+1 byte } memcpy(fl_txdata_frm, rom_buf+send_head, send_size); // set data frame // payload send_head += send_size; fl_wait(tfd3_ua); put_dfrm_ua(send_size, fl_txdata_frm, is_end); // send user data rc = get_sfrm_ua(fl_ua_sfrm, twt7_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } if (fl_st2_ua != flst_ack){ // st2 = ack ? rc = decode_status(fl_st2_ua); // no return rc; // case [d] } if (is_end) // send all user data ? break; // yes //continue; } return flc_no_err; // case [a] } chapter 4 uart communication mode application note u17739ej3v0an 82 4.10 block blank check command 4.10.1 processing sequence chart programmer 78k0/kx2 block blank check command processing sequence t com <1> wait from previous frame reception until next command transmission <2> block blank check command frame transmission reception status [ack/ther than ack] ack time-out error [c] time-out occurs other than ack abnormal termination [b] <4> status frame reception t wt8 number of blocks normal completion [a] <3> time-out check fo r status frame reception status frame received within specified time chapter 4 uart communication mode application note u17739ej3v0an 83 4.10.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the block blank check command is transmi tted by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt8 number of blocks). <4> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [b] 4.10.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed norma lly and all of the specified blocks are blank. parameter error 05h the number of blocks is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] mrg11 error 1bh the specified block in the flash memory is not blank. time-out error [c] ? time-out error of status frame reception has occurred. chapter 4 uart communication mode application note u17739ej3v0an 84 4.10.4 flowchart wait from previous frame reception until next command transmission status = ack? block blank check command processing t com t wt8 number of blocks command frame transmission processing (block blank check) normal completion [a] status frame received? timed out? time-out error [c] abnormal termination [b] no no no yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 85 4.10.5 sample program the following shows a sample program for block blank check command processing. /****************************************************************/ /* */ /* block blank check command */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_blk_blank_chk(u32 top, u32 bottom) { u16 rc; u16 block_num; set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal block_num = get_block_num(top, bottom); // get block num fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_block_blank_chk, 7, fl_cmd_prm); rc = get_sfrm_ua(fl_ua_sfrm, twt8_max * block_num); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 4 uart communication mode application note u17739ej3v0an 86 4.11 silicon signature command 4.11.1 processing sequence chart programmer 78k0/kx2 silicon signature command processing sequence t com normal data frame? [yes/no] <1> wait from previous frame reception until next command transmission <2> silicon signature command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <4> status frame reception time-out error [c] <6> data frame (silicon signature) reception processing data frame error [d] normal completion [a] no yes t wt11 time-out check for status frame reception <3> time-out occurs status frame received within specified time t fd2 time-out check for data frame reception <5> time-out occurs data frame received within specified time chapter 4 uart communication mode application note u17739ej3v0an 87 4.11.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the silicon signature command is transmitt ed by command frame transmission processing. <3> a time-out check is performed from command transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt11 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> a time-out check is performed until dat a frame (silicon signatur e data) reception. if a time-out occurs, a time-out error [c] is returned (time-out time t fd2 ). <6> the received data frame (silic on signature data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 4.11.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the silicon signature was acquired normally. checksum error 07h the checksum of the transmitted command frame is abnormal. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] read error 20h reading of security information failed. time-out error [c] ? time-out error of status frame reception or data frame reception has occurred. data frame error [d] ? the checksum of the data fram e received as silicon signature data is abnormal. chapter 4 uart communication mode application note u17739ej3v0an 88 4.11.4 flowchart wait from previous frame reception until next command transmission status = ack? silicon signature command processing t com t wt11 command frame transmission processing (silicon signature) normal completion [a] data frame (silicon signature) received? timed out? time-out error [c] t fd2 status frame received? timed out? time-out error [c] abnormal termination [b] normal data frame? data frame error [d] yes yes yes yes yes yes no no no no no no chapter 4 uart communication mode application note u17739ej3v0an 89 4.11.5 sample program the following shows a sample program for silicon signature command processing. /****************************************************************/ /* */ /* get silicon signature command */ /* */ /****************************************************************/ /* [i] u8 *sig ... pointer to signature save area */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_getsig(u8 *sig) { u16 rc; fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_get_signature, 1, fl_cmd_prm); // send get signature command rc = get_sfrm_ua(fl_ua_sfrm, twt11_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } rc = get_dfrm_ua(fl_rxdata_frm, tfd2_to); // get status frame if (rc){ // if error return rc; // case [d] } memcpy(sig, fl_rxdata_frm+ofs_sta_pld, fl_rxdata_frm[ofs_len]); // copy signature data return rc; // case [a] } chapter 4 uart communication mode application note u17739ej3v0an 90 4.12 version get command 4.12.1 processing sequence chart programmer 78k0/kx2 version get command processing sequence t com normal data frame? [yes/no] <1> wait from previous frame reception until next command transmission <2> version get command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <4> status frame reception time-out error [c] <6> data frame (version data) reception data frame received within specified time data frame error [d] normal completion [a] no yes t wt12 time-out check for status frame reception <3> time-out occurs status frame received within specified time t fd2 time-out check for data frame reception <5> time-out occurs chapter 4 uart communication mode application note u17739ej3v0an 91 4.12.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the version get command is transmitted by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt12 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> a time-out check is performed until dat a frame (version data) reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t fd2 ). <6> the received data frame (v ersion data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 4.12.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and version data was acquired normally. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? time-out error of status frame reception or data frame reception has occurred. data frame error [d] ? the checksum of the data frame received as version data is abnormal. chapter 4 uart communication mode application note u17739ej3v0an 92 4.12.4 flowchart wait from previous frame reception until next command transmission status = ack? version get command processing t com t wt12 command frame transmission processing (version get) normal completion [a] data frame (version data) received? timed out? time-out error [c] t fd2 status frame received? timed out? time-out error [c] abnormal termination [b] normal data frame? data frame error [d] no no no no no no yes yes yes yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 93 4.12.5 sample program the following shows a sample program for version get command processing. /****************************************************************/ /* */ /* get device/firmware version command */ /* */ /****************************************************************/ /* [i] u8 *buf ... pointer to version date save area */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_getver(u8 *buf) { u16 rc; fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_get_version, 1, fl_cmd_prm); // send get version command rc = get_sfrm_ua(fl_ua_sfrm, twt12_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } rc = get_dfrm_ua(fl_rxdata_frm, tfd2_to); // get data frame if (rc){ return rc; // case [d] } memcpy(buf, fl_rxdata_frm+ofs_sta_pld, dfv_len);// copy version data return rc; // case [a] } chapter 4 uart communication mode application note u17739ej3v0an 94 4.13 checksum command 4.13.1 processing sequence chart programmer 78k0/kx2 checksum command processing sequence t com normal data frame? [yes/no] <1> wait from previous frame reception until next command transmission <2> checksum command frame transmission reception status [ack/other than ack] ack time-out error [c] other than ack abnormal termination [b] <4> status frame reception time-out error [c] <6> data frame (checksum data) reception data frame error [d] normal completion [a] no yes t wt16 time-out check for status frame reception <3> time-out occurs status frame received within specified time t fd1 time-out check for status frame reception <5> time-out occurs data frame received within specified time chapter 4 uart communication mode application note u17739ej3v0an 95 4.13.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the checksum command is transmitted by command frame transmission processing. <3> a time-out check is performed from command transmission until status frame reception. if a time-out occurs, a time-out e rror [c] is returned (time-out time t wt16 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> a time-out check is performed until data frame (checksum data) reception. if a time-out occurs, a time-out error [c] is returned (time-out time t fd1 ). <6> the received data frame (checksum data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 4.13.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and checksum data was acquired normally. parameter error 05h the specified start/ end address is out of the flash memory range, or the specified address is not a fixed address in 2 kb units. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? time-out error of status frame reception or data frame reception has occurred. data frame error [d] ? the checksum of the data frame received as version data is abnormal. chapter 4 uart communication mode application note u17739ej3v0an 96 4.13.4 flowchart wait from previous frame reception until next command transmission status = ack? checksum command processing t com t wt16 command frame transmission processing (checksum) normal completion [a] data frame (checksum data) received? timed out? time-out error [c] t fd1 status frame received? timed out? time-out error [c] abnormal termination [b] normal data frame? data frame error [d] yes yes yes yes yes no no yes no no no no chapter 4 uart communication mode application note u17739ej3v0an 97 4.13.5 sample program the following shows a sample program for checksum command processing. /****************************************************************/ /* */ /* get checksum command */ /* */ /****************************************************************/ /* [i] u16 *sum ... pointer to checksum save area */ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_getsum(u16 *sum, u32 top, u32 bottom) { u16 rc; /************************************************/ /* set params */ /************************************************/ // set params set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal /************************************************/ /* send command */ /************************************************/ fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_get_check_sum, 7, fl_cmd_prm); // send get version command rc = get_sfrm_ua(fl_ua_sfrm, twt16_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* get data frame (checksum data) */ /************************************************/ rc = get_dfrm_ua(fl_rxdata_frm, tfd1_to); // get status frame if (rc){ // if no error, return rc; // case [d] } *sum = (fl_rxdata_frm[ofs_sta_pld] << 8) + fl_rxdata_frm[ofs_sta_pld+1]; // set sum data return rc; // case [a] } chapter 4 uart communication mode application note u17739ej3v0an 98 4.14 security set command 4.14.1 processing sequence chart programmer 78k0/kx2 security set command processing sequence t com t wt13 reception status [ack/other than ack] <4> status frame reception ack <1> wait from previous frame reception until next command transmission <3> time-out check for status frame reception <2> security set command frame transmission abnormal termination [b] other than ack normal completion [a] t fd3 (uart) <5> wait from previous frame reception until data frame transmission <6> data frame (security data) transmission t wt14 <7> time-out check for status frame reception <8> status frame reception reception status [ack/other than ack] abnormal termination [d] other than ack ack <9> time-out check for status frame reception t wt15 <10> status frame reception reception status [ack/other than ack] abnormal termination [e] other than ack ack time-out error [c] time-out occurs status frame received within specified time time-out error [c] time-out occurs status frame received within specified time time-out error [c] time-out occurs status frame received within specified time chapter 4 uart communication mode application note u17739ej3v0an 99 4.14.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the security set command is transmitt ed by command frame transmission processing. <3> a time-out check is performed from comm and transmission until status frame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt13 ). <4> the status code is checked. when st1 = ack: proceeds to <5>. when st1 ack: abnormal termination [b] <5> waits from the previous frame reception until the next data frame transmission (wait time t fd3 (uart) ). <6> the data frame (security setting data) is tr ansmitted by data frame transmission processing. <7> a time-out check is perform ed until status fr ame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt14 ). <8> the status code is checked. when st1 = ack: proceeds to <9>. when st1 ack: abnormal termination [d] <9> a time-out check is perform ed until status fr ame reception. if a time-out occurs, a time-out error [c] is returned (time-out time t wt15 ). <10> the status code is checked. when st1 = ack: normal completion [a] when st1 ack: abnormal termination [e] 4.14.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and security setting was performed normally. parameter error 05h command information (parameter) is not 00h. checksum error 07h the checksum of the transmitted command frame or data frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? time-out error of status frame reception or data frame reception has occurred. flmd error 18h a write error has occurred. abnormal termination [d] write error 1ch a write error has occurr ed (including the case of security data already being set). abnormal termination [e] mrg11 error 1bh an internal verify error has occurred. chapter 4 uart communication mode application note u17739ej3v0an 100 4.14.4 flowchart wait from previous frame reception until next command transmission status = ack? security set command processing t com t wt13 command frame transmission processing (security set) normal completion [a] wait from previous frame reception until next data frame transmission t fd3 data frame transmission processing (security data) status = ack? abnormal termination [d] status = ack? abnormal termination [e] status frame received? timed out? time-out error [c] t wt14 status frame received? timed out? time-out error [c] t wt15 status frame received? timed out? time-out error [c] abnormal termination [b] no no no no no no no no no yes yes yes yes yes yes yes yes yes chapter 4 uart communication mode application note u17739ej3v0an 101 4.14.5 sample program the following shows a sample program for security set command processing. /****************************************************************/ /* */ /* set security flag command */ /* */ /****************************************************************/ /* [i] u8 scf ... security flag data */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_ua_setscf(u8 scf) { u16 rc; /************************************************/ /* set params */ /************************************************/ fl_cmd_prm[0] = 0x00; // "blk" (must be 0x00) fl_cmd_prm[1] = 0x00; // "pag" (must be 0x00) fl_txdata_frm[0] = (scf |= 0b11101000); // "flg" (bit7, 6, 5, 3 must be '1' (to make sure)) fl_txdata_frm[1] = 0x03; // "bot" (fixed 0x03) /************************************************/ /* send command */ /************************************************/ fl_wait(tcom); // wait before sending command put_cmd_ua(fl_com_set_security, 3, fl_cmd_prm); rc = get_sfrm_ua(fl_ua_sfrm, twt13_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send data frame (security setting data) */ /************************************************/ fl_wait(tfd3_ua); chapter 4 uart communication mode application note u17739ej3v0an 102 put_dfrm_ua(2, fl_txdata_frm, true); // send security setting(flag) & bot data rc = get_sfrm_ua(fl_ua_sfrm, twt14_max); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* check internally verify */ /************************************************/ rc = get_sfrm_ua(fl_ua_sfrm, twt15_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } application note u17739ej3v0an 103 chapter 5 3-wire serial i/o communication mode (csi) each of the symbol (t xx and t wtxx ) shown in the flowchart in this chapter is the symbol of characteristic item in chapter 6 flash memory programming parameter characteristics . for each specified value, refer to chapter 6 flash memory programming parameter characteristics . chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 104 5.1 command frame transmission processing flowchart wait between data transmissions (len ? 1) bytes transmitted? command frame transmission processing t dr (csi) command frame header (soh = 01h) transmission wait between data transmissions t dr (csi) data length (len) transmission command number (com) transmission wait between data transmissions t dr (csi) transmits 1-byte parameter wait between data transmissions t dr (csi) checksum data (sum) transmission wait between data transmissions t dr (csi) command frame footer (etx = 03h) transmission end of command frame transmission no yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 105 5.2 data frame transmission processing flowchart wait between data transmissions len bytes transmitted? data frame transmission processing t dr (csi) data frame header (stx = 02h) transmission data length (len) transmission wait between data transmissions t dr (csi) transmits 1-byte data wait between data transmissions t dr (csi) checksum data (sum) transmission wait between data transmissions t dr (csi) last data frame footer (etx = 03h) transmission end of data frame transmission last data frame? transmission of footer other than those of last data frame (etb = 17h) no no yes yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 106 5.3 data frame reception processing flowchart wait between data receptions data frame reception processing t dt (csi) data frame header (stx = 02h) reception data length (len) reception wait between data receptions receives 1-byte data checksum data (sum) reception reception of last data frame footer (etx = 03h) or footer other than those of last data frame (etb = 17h) end of data frame reception t dt (csi) len bytes received? wait between data receptions t dt (csi) wait between data receptions t dt (csi) checksum error? checksum error yes no yes no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 107 5.4 status command 5.4.1 processing sequence chart t wtxx (max.) note programmer 78k0/kx2 status command processing sequence t sf reception status [ack/busy/other than ack, busy] normal completion [a] ack busy no time-out error [c] yes timed out? <2> wait from command frame transmission until status frame acquisition <1> status command frame transmission <3> status frame reception processing abnormal termination [b] other than ack, busy note application specifications diffe r according to execution command. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 108 5.4.2 description of processing sequence <1> the status command is transmitted by command frame transmission processing. <2> waits from command transmission until status frame reception (wait time t sf ). <3> the status code is checked. when st1 = ack: normal completion [a] when st1 = busy: a time-out check is performed ( t wtxx (max.) note ). if the processing is not timed out, the sequence is re-executed from <1>. if a time-out occurs, a time -out error [c] is returned. when st1 ack, busy: abnormal termination [b] note application specifications diffe r according to execution command. 5.4.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the status frame transmi tted from the 78k0/kx2 has been received normally. command error 04h an unsupported command or abnormal frame has been received. parameter error 05h command information (parameter) is invalid. checksum error 07h the data of the frame transmitted from the programmer is abnormal. verify error 0fh a verify error has occu rred for the data of the frame transmitted from the programmer. protect error 10h an attempt was made to execute processing prohibited by the security set command. negative acknowledgment (nack) 15h negative acknowledgment read error 20h reading of security information failed. mrg10 error 1ah an erase error has occurred. mrg11 error 1bh an internal verify error has occurred during data write, or a blank check error has occurred. abnormal termination [b] write error 1ch a write error has occurred. time-out error [c] ? after command transmission, the s pecified time has elapsed but a busy response is still returned. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 109 5.4.4 flowchart command frame transmission processing (status) wait from command frame transmission until status frame reception status frame reception processing status = busy? timed out? normal completion [a] time-out error [c] status command processing t sf t wtxx (max.) note status = ack? abnormal termination [b] no no no yes yes yes note application specifications diffe r according to execution command. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 110 5.4.5 sample program the following shows a sample program for status command processing. /****************************************************************/ /* */ /* get status command (csi) */ /* */ /****************************************************************/ /* [r] u16 ... decoded status or error code */ /* */ /* (see fl.h/fl-proto.h & */ /* definition of decode_status() in fl.c) */ /****************************************************************/ static u16 fl_csi_getstatus(u32 limit) { u16 rc; start_flto(limit); while(1){ put_cmd_csi(fl_com_get_sta, 1, fl_cmd_prm); // send "status" command // frame fl_wait(tsf); // wait rc = get_sfrm_csi(fl_rxdata_frm); // get status frame switch(rc){ case flc_busy: if (check_flto()) // time out ? return flc_dfto_err; // yes, time-out // case [c] continue; // no, retry default: // checksum error return rc; case flc_no_err: // no error break; } if (fl_st1 == flst_busy){ // st1 = busy if (check_flto()) // time out ? return flc_dfto_err; // yes, time-out // case [c] continue; // no, retry } break; // ack or other error (but busy) } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 111 rc = decode_status(fl_st1); // decode status to return code // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 112 5.5 reset command 5.5.1 processing sequence chart programmer 78k0/kx2 reset command processing sequence t com t wt0 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion [a] normal completion abnormal termination no abnormal termination [b] yes retry count over? note wait from previous frame reception until next command transmission <1> <3> wait from command frame transmission until status check time-out error [c] time-out error <2> reset command frame transmission note do not exceed the retry count for the reset command transmission (up to 16 times). chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 113 5.5.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the reset command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt0 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: normal completion [a] when the processing ends abnormally: the sequence is re-exe cuted from <1> if the retry count is not over. if the retry count is over, the processing ends abnormally [b]. when a time-out error occurs: a ti me-out error [c] is returned. 5.5.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and synchronization between the programmer and the 78k0/kx2 has been established. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? status check processing te rminated with time-out. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 114 5.5.4 flowchart command frame transmission processing (reset) wait from previous frame reception until next command transmission wait from command frame transmission until status check status check processing result of status check processing = abnormal termination? retry count over? normal completion [a] reset command processing t com t wt0 result of status check processing = time-out error? abnormal termination [b] time-out error [c] yes yes yes no no no (normal completion) chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 115 5.5.5 sample program the following shows a sample program for reset command processing. /****************************************************************/ /* */ /* reset command (csi) */ /* */ /****************************************************************/ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_reset(void) { u16 rc; u32 retry; for (retry = 0; retry < trs; retry++){ fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_reset, 1, fl_cmd_prm); // send "reset" command frame fl_wait(twt0); rc = fl_csi_getstatus(twt0_to); // get status if (rc == flc_dfto_err) // timeout error ? break; // yes // case [c] if (rc == flc_ack) // ack ? break; // yes // case [a] //continue; // case [b] (if exit from loop) } // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 116 5.6 oscillating frequency set command execution of this command is not nec essary during csi communication (if ex ecution of this command is required during csi communication according to the progra mmer specifications, set the frequency to 8 mhz). 5.6.1 processing sequence chart programmer 78k0/kx2 oscillating frequency set command processing sequence t com t wt9 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion [a] normal completion abnormal termination abnormal termination [b] <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> oscillating frequency set command frame transmission time-out error time-out error [c] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 117 5.6.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the oscillating frequency set command is transmi tted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt9 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: normal completion [a] when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. 5.6.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the operating frequency was correctly set to the 78k0/kx2. parameter error 05h the oscillation frequency value is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 118 5.6.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? oscillating frequency set command processing t com t wt9 command frame transmission processing (oscillating frequency set) status check processing normal completion [a] time-out error time-out error [c] abnormal termination [b] yes yes no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 119 5.6.5 sample program the following shows a sample program for oscillating frequency set command processing. /****************************************************************/ /* */ /* set flash device clock value command (csi) */ /* */ /****************************************************************/ /* [i] u8 clk[4] ... frequency data(d1-d4) */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_setclk(u8 clk[]) { u16 rc; fl_cmd_prm[0] = clk[0]; // "d01" fl_cmd_prm[1] = clk[1]; // "d02" fl_cmd_prm[2] = clk[2]; // "d03" fl_cmd_prm[3] = clk[3]; // "d04" fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_set_osc_freq, 5, fl_cmd_prm); // send "oscillation frequency set" command fl_wait(twt9); rc = fl_csi_getstatus(twt9_to); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 120 5.7 chip erase command 5.7.1 processing sequence chart programmer 78k0/kx2 chip erase command processing sequence t com t wt1 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing time-out error normal completion normal completion [a] <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> chip erase command frame transmission abnormal termination [b] abnormal termination time-out error [c] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 121 5.7.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the chip erase command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt1 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: normal completion [a] when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. 5.7.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and chip erase was performed normally. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h chip erase is pr ohibited by the security setting. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] erase error 1ah an erase error has occurred. time-out error [c] ? the status frame was not received within the specified time. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 122 5.7.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? chip erase command processing t com t wt1 command frame transmission processing (chip erase) status check processing normal completion [a] time-out error? abnormal termination [b] time-out error [c] no no yes yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 123 5.7.5 sample program the following shows a sample program for chip erase command processing. /****************************************************************/ /* */ /* erase all(chip) command (csi) */ /* */ /****************************************************************/ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_erase_all(void) { u16 rc; fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_erase_chip, 1, fl_cmd_prm); // send "chip erase" command fl_wait(twt1); rc = fl_csi_getstatus(twt1_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 124 5.8 block erase command 5.8.1 processing sequence chart programmer 78k0/kx2 block erase command processing sequence t com t wt2 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing time-out error normal completion <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> block erase command frame transmission abnormal termination [b] abnormal termination time-out error [c] normal completion [a] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 125 5.8.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the block erase command is transmitted by command frame transmission processing. <3> waits until status frame acquisition (wait time t wt2 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: normal completion [a] when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. 5.8.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and block erase was performed normally. parameter error 05h the number of blocks is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h write, block erase, or chip erase is prohibited by the security setting. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] erase error 1ah an erase error has occurred. time-out error [c] ? the status frame was not received within the specified time. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 126 5.8.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? block erase command processing t com t wt2 command frame transmission processing (block erase) status check processing normal completion [a] time-out error? time-out error [c] abnormal termination [b] yes yes no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 127 5.8.5 sample program the following shows a sample program for block erase command processing. /****************************************************************/ /* */ /* erase block command (csi) */ /* */ /****************************************************************/ /* [i] u16 sblk ... start block to erase (0...255) */ /* [i] u16 eblk ... end block to erase (0...255) */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_erase_blk(u16 sblk, u16 eblk) { u16 rc; u32 wt2, wt2_max; u32 top, bottom; top = get_top_addr(sblk); // get start address of start block bottom = get_bottom_addr(eblk); // get end address of end block set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal wt2 = make_wt2(sblk, eblk); wt2_max = make_wt2_max(sblk, eblk); fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_erase_block, 7, fl_cmd_prm); // send "block erase" command fl_wait(wt2); rc = fl_csi_getstatus(wt2_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 128 5.9 programming command 5.9.1 processing sequence chart programmer 78k0/kx2 programming command processing sequence t com t wt3 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> programming command frame transmission abnormal termination [b] abnormal termination normal completion [a] t fd3 <6> wait from previous frame reception until next data frame transmission <7> data frame (user data) transmission t wt4 <8> wait during status check <10> result of status check processing (st1/ st2) reception status (st1) [normal completion/ abnormal termination/ time-out error] time- out error [c] time-out error reception status (st2) [ack/other than ack] normal completion abnormal termination [d] other than ack ack all data frames transmitted? [yes/no] go to <6> no <11> wait during status check (internal verify) t wt5 number of blocks yes <13> result of status check processing result [normal completion/ abnormal termination/ time-out error] time-out error [c] time-out error normal completion <9> status check processing <12> status check processing time-out error [c] time- out error abnormal termination [b] abnormal termination abnormal termination [e] abnormal termination chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 129 5.9.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the programming command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt3 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits until the next data frame transmission (wait time t fd3 ). <7> user data to be written to the 78k0/kx2 flash memo ry is transmitted by data fr ame transmission processing. <8> waits from data frame (user data) transmi ssion until status check processing (wait time t wt4 ). <9> the status frame is acquir ed by status check processing. <10> the following processing is performed according to the result of status c heck processing (status code (st1/st2)) (also refer to the processing sequence chart and flowchart). when st1 = abnormal termination: abnormal termination [b] when st1 = time-out error: a ti me-out error [c] is returned. when st1 = normal completion: the following proce ssing is performed according to the st2 value. ? when st2 ack: abnormal termination [d] ? when st2 = ack: proceeds to <11> when transmi ssion of all of the user data is completed. if there still remain user data to be tr ansmitted, the processing re-executes the sequence from <6>. <11> waits until status che ck processing (time-out time t wt5 number of blocks). <12> the status frame is acquir ed by status check processing. <13> the following processing is performed accordi ng to the result of status check processing. when the processing ends normally: normal completion [a] (indicating that the internal ve rify check has performed normally after completion of write) when the processing ends abnormally: abnormal termination [e] (indicating that the internal veri fy check has not performed normally after completion of write) when a time-out error occurs: a ti me-out error [c] is returned. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 130 5.9.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed nor mally and the user data was written normally. parameter error 05h the specified start/ end address is out of the flash memory range, or is not a multiple of 8. checksum error 07h the checksum of the transmitted command frame is abnormal. protect error 10h write is prohi bited by the security setting. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. abnormal termination [d] write error 1ch (st2) a write error has occurred. abnormal termination [e] mrg11 error 1bh an internal verify error has occurred. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 131 5.9.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? programming command processing t com t wt3 command frame transmission processing (programming) status check processing normal completion [a] time-out error? wait from previous frame reception until next command transmission t fd3 data frame transmission processing (user program) wait from data frame transmission until status check t wt4 status check processing time-out error? time-out error [c] normal completion? st2 = ack? all data frame s transmitted? wait during status check (internal verify) t wt5 number of blocks status check processing time-out error? time- out error [c] normal completion? abnormal termination [e] time-out error [c] abnormal termination [b] abnormal termination [b] abnormal termination [d] no yes yes yes yes yes yes yes yes no no no no no no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 132 5.9.5 sample program the following shows a sample program for programming command processing. /****************************************************************/ /* */ /* write command (csi) */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_write(u32 top, u32 bottom) { u16 rc; u32 send_head, send_size; bool is_end; u16 block_num; // set params set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal block_num = get_block_num(top, bottom); // get block num /************************************************/ /* send command & check status */ /************************************************/ fl_wait(tcom); put_cmd_csi(fl_com_write, 7, fl_cmd_prm); // send "programming" command fl_wait(twt3); rc = fl_csi_getstatus(twt3_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send user data */ /************************************************/ send_head = top; while(1){ if ((bottom - send_head) > 256){ // rest size > 256 ? is_end = false; // yes, not end frame send_size = 256; // transmit size = 256 byte chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 133 } else{ is_end = true; send_size = bottom - send_head + 1; // transmit size = (bottom - send_head)+1 byte } memcpy(fl_txdata_frm, rom_buf+send_head, send_size); // set data frame payload send_head += send_size; fl_wait(tfd3_csi); // wait before sending data frame put_dfrm_csi(send_size, fl_txdata_frm, is_end); // send data frame (user data) fl_wait(twt4); // wait rc = fl_csi_getstatus(twt4_max); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } if (fl_st2 != flst_ack){ // st2 = ack ? rc = decode_status(fl_st2); // no return rc; // case [d] } if (is_end) // send all user data ? break; // yes //continue; } /************************************************/ /* check internally verify */ /************************************************/ fl_wait(twt5 * block_num); // wait rc = fl_csi_getstatus(twt5_max * block_num); // get status frame // switch(rc) { // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [e] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 134 5.10 verify command 5.10.1 processing sequence chart programmer 78k0/kx2 verify command processing sequence t com t wt6 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> verify command frame transmission abnormal termination [b] abnormal termination normal completion [a] t fd3 (csi) <6> wait from previous frame reception until next command transmission <7> data frame (user data for verify) transmission t wt7 <8> wait during status check (internal verify) <10> result of status check processing (st1/st2) reception status (st1) [normal completion/ abnormal termination/ time-out error] abnormal termination [b] abnormal termination reception status (st2) [ack/other than ack] normal completion abnormal termination [d] other than ack ack all data frames transmitted? [yes/no] go to <6> no yes <9> status check processing time-out error [c] time-out error time-out error [c] time-out error chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 135 5.10.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the verify command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt6 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits from the previous frame reception until the next data frame transmission (wait time t fd3 ). <7> user data for verifying is transmitt ed by data frame transmission processing. <8> waits from data frame transmission unt il status check processing (wait time t wt7 ). <9> the status frame is acquir ed by status check processing. <10> the following processing is performed according to the result of status c heck processing (status code (st1/st2)) (also refer to the processing sequence chart and flowchart). when st1 = abnormal termination: abnormal termination [b] when st1 = time-out error: a ti me-out error [c] is returned. when st1 = normal completion: the following proce ssing is performed according to the st2 value. ? when st2 ack: abnormal termination [d] ? when st2 = ack: if transmission of all data fram es is completed, the processing ends normally [a]. if there still remain data frames to be transmitted, the processing re-executes the sequence from <6>. 5.10.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the verify was completed normally. parameter error 05h the specified start/ end address is out of the flash memory range, or the specified address is not a fixed address in 2 kb units. checksum error 07h the checksum of the transmitted command frame or data frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. abnormal termination [d] verify error 0fh (st2) the verify has failed, or another error has occurred. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 136 5.10.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? verify command processing t com t wt6 command frame transmission processing (verify) status check processing time-out error? wait from previous frame reception until next data frame transmission t fd3 (csi) data frame transmission processing (user program) wait from data frame transmission until status check t wt7 status check processing time-out error? normal completion? st2 = ack? all data frames transmitted? normal completion [a] time-out error [c] abnormal termination [b] time-out error [c] abnormal termination [b] abnormal termination [d] no no no no no no yes yes yes yes yes yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 137 5.10.5 sample program the following shows a sample program for verify command processing. /****************************************************************/ /* */ /* verify command (csi) */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_verify(u32 top, u32 bottom) { u16 rc; u32 send_head, send_size; bool is_end; // set params set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal /************************************************/ /* send command & check status */ /************************************************/ fl_wait(tcom); put_cmd_csi(fl_com_verify, 7, fl_cmd_prm); // send "verify" command fl_wait(twt6); rc = fl_csi_getstatus(twt6_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send user data */ /************************************************/ send_head = top; while(1){ if ((bottom - send_head) > 256){ // rest size > 256 ? is_end = false; // yes, not end frame send_size = 256; // transmit size = 256 byte } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 138 else{ is_end = true; send_size = bottom - send_head + 1; // transmit size = (bottom - send_head)+1 byte } memcpy(fl_txdata_frm, rom_buf+send_head, send_size); // set data // frame payload send_head += send_size; fl_wait(tfd3_csi); // wait before sending data frame put_dfrm_csi(send_size, fl_txdata_frm, is_end); // send data frame fl_wait(twt7); // wait rc = fl_csi_getstatus(twt7_max); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } if (fl_st2 != flst_ack){ // st2 = ack ? rc = decode_status(fl_st2); // no return rc; // case [d] } if (is_end) // send all user data ? break; // yes //continue; } return flc_no_err; // case [a] } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 139 5.11 block blank check command 5.11.1 processing sequence chart programmer 78k0/kx2 block blank check command processing sequence t com t wt8 number of blocks <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing time-out error normal completion <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> block blank check command frame transmission abnormal termination [b] abnormal termination time-out error[c] normal completion [a] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 140 5.11.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the block blank check command is transmi tted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt8 number of blocks). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when a time-out error occurs: a ti me-out error [c] is returned. when the processing ends abnormally: abnormal termination [b] when the processing ends normally: normal completion [a] 5.11.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed norma lly and all of the specified blocks are blank. parameter error 05h the number of blocks is out of range. checksum error 07h the checksum of the transmitted command frame is abnormal. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] mrg11 error 1bh the specified block in the flash memory is not blank. time-out error [c] ? the status frame was not received within the specified time. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 141 5.11.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? block blank check command processing t com t wt8 number of blocks command frame transmission processing (block blank check) status check processing normal completion [a] time-out error? time-out error [c] abnormal termination [b] yes yes no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 142 5.11.5 sample program the following shows a sample program for block blank check command processing. /****************************************************************/ /* */ /* block blank check command (csi) */ /* */ /****************************************************************/ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_blk_blank_chk(u32 top, u32 bottom) { u16 rc; u16 block_num; set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal block_num = get_block_num(top, bottom); // get block num fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_block_blank_chk, 7, fl_cmd_prm); // send "block blank check" command fl_wait(twt8 * block_num); rc = fl_csi_getstatus(twt8_max * block_num); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 143 5.12 silicon signature command 5.12.1 processing sequence chart programmer 78k0/kx2 silicon signature command processing sequence t com t wt11 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion abnormal termination abnormal termination [b] <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> silicon signature command frame transmission time-out error t fd2 <6> wait from previous frame reception until next data frame transmission <7> data frame (silicon signature) reception processing normal data frame? [yes/no] time-out error [c] data frame error [d] normal completion [a] no yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 144 5.12.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the silicon signature command is transmitt ed by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt11 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits from the previous frame recepti on until the next command transmission (wait time t fd2 ). <7> the received data frame (silic on signature data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 5.12.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and the silicon signature was acquired normally. checksum error 07h the checksum of the transmitted command frame is abnormal. negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). abnormal termination [b] read error 20h reading of security information failed. time-out error [c] ? the status frame was not received within the specified time. data frame error [d] ? the checksum of the data fram e received as silicon signature data is abnormal. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 145 5.12.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? silicon signature command processing t com t wt11 command frame transmission processing (silicon signature) status check processing normal completion [a] time-out error? wait from previous frame reception until next data frame reception t fd2 data frame reception processing normal data frame? data frame error [d] time-out error [c] abnormal termination [b] no no no yes yes yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 146 5.12.5 sample program the following shows a sample program for silicon signature command processing. /****************************************************************/ /* */ /* get silicon signature command (csi) */ /* */ /****************************************************************/ /* [i] u8 *sig ... pointer to signature save area */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_getsig(u8 *sig) { u16 rc; fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_get_signature, 1, fl_cmd_prm); // send "silicon signature" command fl_wait(twt11); rc = fl_csi_getstatus(twt11_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } fl_wait(tfd2_sig); // wait before getting data frame rc = get_dfrm_csi(fl_rxdata_frm); // get data frame (signature data) if (rc){ // if no error, return rc; // case [d] } memcpy(sig, fl_rxdata_frm+ofs_sta_pld, fl_rxdata_frm[ofs_len]); // copy signature data return rc; // case [a] } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 147 5.13 version get command 5.13.1 processing sequence chart programmer 78k0/kx2 version get command processing sequence t com t wt12 <4> status check procesing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion abnormal termination [b] <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> version get command frame transmission time-out error t fd2 <6> wait from previous frame reception until next data frame reception <7> status frame (version data) reception processing normal data frame? [yes/no] data frame error [d] normal completion [a] no yes abnormal termination time-out error [c] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 148 5.13.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the version get command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt12 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits from the previous frame recepti on until the next command transmission (wait time t fd2 ). <7> the received data frame (v ersion data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 5.13.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and version data was acquired normally. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. data frame error [d] ? the checksum of the data frame received as version data is abnormal. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 149 5.13.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? version get command processing t com t wt12 command frame transmission processing (version get) status check processing normal completion [a] time-out error? wait from previous frame reception until next data frame reception t fd2 data frame reception processing normal data frame? data frame error [d] time-out error [c] abnormal termination [b] yes yes yes no no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 150 5.13.5 sample program the following shows a sample program for version get command processing. /****************************************************************/ /* */ /* get device/firmware version command (csi) */ /* */ /****************************************************************/ /* [i] u8 *buf ... pointer to version date save area */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_getver(u8 *buf) { u16 rc; fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_get_version, 1, fl_cmd_prm); // send "version get" command fl_wait(twt12); rc = fl_csi_getstatus(twt12_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } fl_wait(tfd2_vg); // wait before getting data frame rc = get_dfrm_csi(fl_rxdata_frm); // get version data if (rc){ // if no error, return rc; // case [d] } memcpy(buf, fl_rxdata_frm+ofs_sta_pld, dfv_len);// copy version data return rc; // case [a] } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 151 5.14 checksum command 5.14.1 processing sequence chart programmer 78k0/kx2 checksum command processing sequence t com t wt16 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion abnormal termination abnormal termination [b] <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> checksum command frame transmission time-out error t fd1 <6> wait from previous frame reception until next data frame reception <7> data frame (checksum data) reception processing normal data frame? [yes/no] time-out error [c] data frame error [d] normal completion [a] no yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 152 5.14.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the checksum command is transmitted by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt16 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits from the previous frame recepti on until the next command transmission (wait time t fd1 ). <7> the received data frame (checksum data) is checked. if data frame is normal: normal completion [a] if data frame is abnormal: data frame error [d] 5.14.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and checksum data was acquired normally. parameter error 05h the specified start/ end address is out of the flash memory range, or the specified address is not a fixed address in 2 kb units. checksum error 07h the checksum of the transmitted command frame is abnormal. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. data frame error [d] ? the checksum of the data frame received as version data is abnormal. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 153 5.14.4 flowchart wait from previous frame reception until next command reception wait from command frame transmission until status check normal completion? checksum command processing t com t wt16 command frame transmission processing (checksum) status check processing normal completion [a] time-out error? wait from previous frame reception until next data frame reception t fd1 data frame reception processing normal data frame? data frame error [d] time-out error [c] abnormal termination [b] no yes no no yes yes chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 154 5.14.5 sample program the following shows a sample program for checksum command processing. /****************************************************************/ /* */ /* get checksum command (csi) */ /* */ /****************************************************************/ /* [i] u16 *sum ... pointer to checksum save area */ /* [i] u32 top ... start address */ /* [i] u32 bottom ... end address */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_getsum(u16 *sum, u32 top, u32 bottom) { u16 rc; u16 block_num; /************************************************/ /* set params */ /************************************************/ // set params set_range_prm(fl_cmd_prm, top, bottom); // set sah/sam/sal, eah/eam/eal block_num = get_block_num(top, bottom); // get block num /************************************************/ /* send command */ /************************************************/ fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_get_check_sum, 7, fl_cmd_prm); // send "checksum" command fl_wait(twt16); rc = fl_csi_getstatus(twt16_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* get data frame (checksum data) */ /************************************************/ fl_wait(tfd1 * block_num); // wait before getting data frame chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 155 rc = get_dfrm_csi(fl_rxdata_frm); // get data frame(version data) if (rc){ // if error, return rc; // case [d] } *sum = (fl_rxdata_frm[ofs_sta_pld] << 8) + fl_rxdata_frm[ofs_sta_pld+1]; // set sum data return rc; // case [a] } chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 156 5.15 security set command 5.15.1 processing sequence chart programmer 78k0/kx2 security set command processing sequence t com t wt13 <4> status check processing result [normal completion/ abnormal termination/ time-out error] <5> result of status check processing normal completion <1> wait from previous frame reception until next command transmission <3> wait from command frame transmission until status check <2> security set command frame transmission abnormal termination [b] abnormal termination abnormal termination [b] t fd3 (csi) <6> wait from previous frame reception until next data frame transmission <7> data frame (security data) transmission t wt14 <8> wait from data frame transmission until status check <10> result of status check processing result [normal completion/ abnormal termination/ time-out error] time-out error abnormal termination [b] abnormal termination normal completion <11> wait during status check (internal verify) t wt15 <13> result of status check processing result [normal completion/ abnormal termination/ time-out error] time-out error [c] time-out error abnormal termination normal completion <9> status check processing <12> status check processing time-out error [c] time-out error time-out error [c] normal completion [a] chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 157 5.15.2 description of processing sequence <1> waits from the previous frame recepti on until the next command transmission (wait time t com ). <2> the security set command is transmitt ed by command frame transmission processing. <3> waits from command transmission until status check processing (wait time t wt13 ). <4> the status frame is acquir ed by status check processing. <5> the following processing is performed according to the result of status check processing. when the processing ends normally: proceeds to <6>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <6> waits from the previous frame recepti on until the data frame transmission (wait time t fd3 (csi) ). <7> the data frame (security setting data) is tr ansmitted by data frame transmission processing. <8> waits from data frame transmission unt il status check processing (wait time t wt14 ). <9> the status frame is acquir ed by status check processing. <10> the following processing is performed accordi ng to the result of status check processing. when the processing ends normally: proceeds to <11>. when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. <11> waits until status acquisition (compl etion of internal verify) (wait time t wt15 ). <12> the status frame is acquir ed by status check processing. <13> the following processing is performed accordi ng to the result of status check processing. when the processing ends normally: normal completion [a] when the processing ends abnormally: abnormal termination [b] when a time-out error occurs: a ti me-out error [c] is returned. 5.15.3 status at processing completion status at processing completion status code description normal completion [a] normal acknowledgment (ack) 06h the command was executed normally and security setting was performed normally. parameter error 05h command information (parameter) is not 00h. checksum error 07h the checksum of the transmitted command frame or data frame is abnormal. write error 1ch security data has al ready been set, or a write error has occurred. abnormal termination [b] negative acknowledgment (nack) 15h command frame data is abnormal (such as invalid data length (len) or no etx). time-out error [c] ? the status frame was not received within the specified time. chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 158 5.15.4 flowchart wait from previous frame reception until next command transmission wait from command frame transmission until status check normal completion? security set command processing t com t wt13 command frame transmission processing (security set) status check processing normal completion [a] time-out error? wait from previous frame reception until next data frame transmission t fd3 data frame transmission processing (internal verify) wait from data frame transmission until status check t wt14 status check processing time-out error? normal completion? wait during status check (internal verify) t wt15 status check processing time-out error? normal completion? abnormal termination [b] time-out error [c] abnormal termination [b] time-out error [c] abnormal termination [b] time-out error [c] yes yes yes yes yes yes no no no no no no chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 159 5.15.5 sample program the following shows a sample program for security set command processing. /****************************************************************/ /* */ /* set security flag command (csi) */ /* */ /****************************************************************/ /* [i] u8 scf ... security flag data */ /* [r] u16 ... error code */ /****************************************************************/ u16 fl_csi_setscf(u8 scf) { u16 rc; /********************************************************/ /* set params */ /********************************************************/ fl_cmd_prm[0] = 0x00; // "blk" (must be 0x00) fl_cmd_prm[1] = 0x00; // "pag" (must be 0x00) fl_txdata_frm[0] = (scf |= 0b11101000); // "flg" (upper 5bits must be '1' (to make sure)) fl_txdata_frm[1] = 0x03; // "bot" (fixed 0x03) /************************************************/ /* send command */ /************************************************/ fl_wait(tcom); // wait before sending command frame put_cmd_csi(fl_com_set_security, 3, fl_cmd_prm); // send "security set" command fl_wait(twt13); // wait rc = fl_csi_getstatus(twt13_to); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* send data frame (security setting data) */ /************************************************/ fl_wait(tfd3_csi); // wait before getting data frame chapter 5 3-wire serial i/o communication mode (csi) application note u17739ej3v0an 160 put_dfrm_csi(2, fl_txdata_frm, true); // send data frame(security data) fl_wait(twt14); rc = fl_csi_getstatus(twt14_max); // get status frame switch(rc) { case flc_no_err: break; // continue // case flc_dfto_err: return rc; break; // case [c] default: return rc; break; // case [b] } /************************************************/ /* check internally verify */ /************************************************/ fl_wait(twt15); rc = fl_csi_getstatus(twt15_max); // get status frame // switch(rc) { // // case flc_no_err: return rc; break; // case [a] // case flc_dfto_err: return rc; break; // case [c] // default: return rc; break; // case [b] // } return rc; } application note u17739ej3v0an 161 chapter 6 flash memory progra mming parameter characteristics this chapter describes the paramet er characteristics between the progr ammer and the 78k0/kx2 in the flash memory programming mode. be sure to refer to the user?s manual of the 78k0/kx2 for electrical specifications when designing a programmer. 6.1 flash memory programming parameter characteristics of expanded specification products ( pd78f05xxa) 6.1.1 basic characteristics parameter condition symbol min. typ. max. unit 78k0/kx2 operating clock in flash memory programming mode internal high-speed oscillation clock f rh 7.6 8 8.4 x1 clock f x 2 20 external main system clock during uart communication f exclk 2 20 mhz 6.1.2 flash memory progr amming mode setting time parameter symbol min. typ. max. v dd to flmd0 t dp 1 ms flmd0 to reset t pr 2 ms count start time from reset to flmd0 note 1 t rp 59,327/f rh count finish time from reset to flmd0 note 1 t rpe 238,414/f rh flmd0 counter high-level/low-level width t pw 10 s 100 s wait for reset command (csi) note 1 t rc 444,463/f rh x1 clock 444,463/f rh + 2 16 /f x wait for low-level data 1 (uart) note 1 external main system clock t r1 444,463/f rh wait for low-level data 2 (uart) t 12 15,000/f rh wait for read command (uart) t 2c 15,000/f rh width of low-level data 1/2 note 2 t l1 , t l2 note 2 flmd0 counter rise/fall time ? 1 s reset low level width (reset to reset ) note 3 t rst 1,950 ms notes 1. (59,327/f rh + 238,414/f rh )/2 is recommended as the standard value for the flmd0 pulse input timing. 2. the low-level width is the same as the 00h data width at 9,600 bps. 3. when the mode is switched from the normal operating mode to the flash memory programming mode after the microcontroller is powered on (reset is rel eased), be sure to wait for the period of this parameter at minimum before reset for mode switching after power-on (reset release). (remarks are carried over to the next page.) chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 162 remarks 1. calculate the paramet ers assuming that f rh = 8 mhz. 2. the waits are defined as follows. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 163 command symbol serial i/f min. max. csi 172/f rh reset t wt0 uart note 1 chip erase t wt1 ? 857,883/f rh + 44,160 total number of blocks/f rh 186,444,400/f rh + 11,304,960 total number of blocks/f rh block erase t wt2 note 2 ? 214,714/f rh execution count of simultaneous selection and erasure + 44,160/f rh number of blocks to be erased 54,582,372/f rh execution count of simultaneous selection and erasure + 11,304,960/f rh number of blocks to be erased csi 1,506/f rh t wt3 uart note 1 t wt4 note 3 ? 72,412/f rh 893,355/f rh block 0 100,407/f rh 132,144,427/f rh csi block 1 to 127 100,407/f rh 102,178/f rh block 0 note 1 132,144,427/f rh programming t wt5 note 4 uart block 1 to 127 note 1 102,178/f rh csi 686/f rh t wt6 uart note 1 csi 12,827/f rh verify t wt7 note 3 uart note 1 csi 45,870/f rh 55,044/f rh block blank check t wt8 note 4 uart note 1 55,044/f rh csi 1,238/f rh oscillating frequency set t wt9 uart note 1 csi 1,233/f rh silicon signature t wt11 uart note 1 csi 252/f rh version get t wt12 uart note 1 csi 975/f rh t wt13 uart note 1 t wt14 ? 275,518/f rh 66,005,812/f rh csi 368,277/f rh 66,018,156/f rh security set t wt15 uart note 1 66,018,156/f rh csi 583/f rh checksum t wt16 uart note 1 notes 1. reception must be enabled for the pr ogrammer before command transmission. 2. see 6.3 simultaneous selection and erasu re performed by block erase command for the calculation method of the execution count of simult aneous selection and erasure. 3. time for 256-byte data transmission 4. time for one block transmission remarks 1. calculate the paramet ers assuming that f rh = 8 mhz. 2. the waits are defined as follows. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 164 the programmer must repeat t he status check for the period of the max. time (or about 3 seconds, if the max. time is not specified). 6.2 flash memory programming parameter ch aracteristics of conventional-specification products ( pd78f05xx) 6.2.1 basic characteristics parameter condition symbol min. typ. max. unit 78k0/kx2 operating clock in flash memory programming mode internal high-speed oscillation clock f rh 7.6 8 8.4 x1 clock f x 2 20 external main system clock during uart communication f exclk 2 20 mhz 6.2.2 flash memory progr amming mode setting time parameter symbol min. typ. max. v dd to flmd0 t dp 1 ms flmd0 to reset t pr 2 ms count start time from reset to flmd0 note 1 t rp 59,327/f rh count finish time from reset to flmd0 note 1 t rpe 238,414/f rh flmd0 counter high-level/low-level width t pw 10 s 100 s wait for reset command (csi) t rc 444,463/f rh x1 clock 444,463/f rh + 2 16 /f x wait for low-level data 1 (uart) external main system clock t r1 444,463/f rh wait for low-level data 2 (uart) t 12 15,000/f rh wait for read command (uart) t 2c 15,000/f rh width of low-level data 1/2 note 2 t l1 , t l2 note 2 flmd0 counter rise/fall time ? 1 s reset low level width (reset to reset ) note 3 t rst 1,950 ms notes 1. (59,327/f rh + 238,414/f rh )/2 is recommended as the standard value for the flmd0 pulse input timing. 2. the low-level width is the same as the 00h data width at 9,600 bps, and the value described here is half that data width. 3. when the mode is switched from the normal operating mode to the flash memory programming mode after the microcontroller is powered on (reset is rel eased), be sure to wait for the period of this parameter at minimum before reset for mode switching after power-on (reset release). remarks 1. calculate the paramet ers assuming that f rh = 8 mhz. 2. the waits are defined as follows. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 165 6.2.3 programming characteristics wait condition symbol serial i/f min. max. csi 64/f rh data frame reception t dr uart 74/f rh csi 88/f rh between data frame transmission/reception data frame transmission t dt uart 0 note 1 from status command frame reception until status frame transmission ? t sf csi 166/f rh csi 54,368/f rh from status frame transmission until data frame transmission (1) ? t fd1 note 2 uart 0 note 1 silicon signature data 321/f rh version data csi 136/f rh from status frame transmission until data frame transmission (2) ? t fd2 uart 0 note 1 csi 163/f rh from status frame transmission until data frame reception ? t fd3 uart 101/f rh csi 64/f rh from status frame transmission until command frame reception ? t com uart 71/f rh notes 1. when successive reception is enabled for the programmer 2. time for one block transmission remarks 1. calculate the paramet ers assuming that f rh = 8 mhz. 2. the waits are defined as follows. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 166 command symbol serial i/f min. max. csi 172/f rh reset t wt0 uart note 1 chip erase t wt1 ? 857,883/f rh + 44,160 total number of blocks/f rh 186,444,400/f rh + 11,304,960 total number of blocks/f rh block erase t wt2 note 2 ? 214,714/f rh execution count of simultaneous selection and erasure + 44,160/f rh number of blocks to be erased 54,582,372/f rh execution count of simultaneous selection and erasure + 11,304,960/f rh number of blocks to be erased csi 1,348/f rh t wt3 uart note 1 t wt4 note 3 ? 68,118/f rh 397,587/f rh block 0 100,407/f rh 132,144,427/f rh csi block 1 to 127 100,407/f rh 102,178/f rh block 0 note 1 132,144,427/f rh programming t wt5 note 4 uart block 1 to 127 note 1 102,178/f rh csi 686/f rh t wt6 uart note 1 csi 12,827/f rh verify t wt7 note 3 uart note 1 csi 45,835/f rh 55,044/f rh block blank check t wt8 note 4 uart note 1 55,044/f rh csi 1,127/f rh oscillating frequency set t wt9 uart note 1 csi 1,233/f rh silicon signature t wt11 uart note 1 csi 242/f rh version get t wt12 uart note 1 csi 923/f rh t wt13 uart note 1 t wt14 ? 275,518/f rh 66,005,812/f rh csi 368,277/f rh 66,018,156/f rh security set t wt15 uart note 1 66,018,156/f rh csi 583/f rh checksum t wt16 uart note 1 notes 1. reception must be enabled for the pr ogrammer before command transmission. 2. see 6.3 simultaneous selection and erasu re performed by block erase command for the calculation method of the execution count of simult aneous selection and erasure. 3. time for 256-byte data transmission 4. time for one block transmission remarks 1. calculate the paramet ers assuming that f rh = 8 mhz. 2. the waits are defined as follows. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 167 the programmer must repeat t he status check for the period of the max. time (or about 3 seconds, if the max. time is not specified). 6.3 simultaneous selection and erasure performed by block erase command the block erase command of the 78k0/ kx2 is executed by repeating ?simul taneous selection and erasure?, which erases multiple blocks simultaneously. the wait time inserted during block er ase command execution is therefore equal to the to tal execution time of ?simultaneous selection and erasure?. to calculate the ?total ex ecution time of simultaneous selection and erasure?, the execut ion count (m) of the simultaneous selection and erasure must first be calculated. ?m? is calculated by obtaining the number of blocks to be erased simultaneously (number of blocks to be selected and erased simultaneously). the following describes the method fo r calculating the number of blocks to be selected and erased simultaneously and the execution count (m). (1) calculation of number of blocks to be selected and erased simultaneously the number of blocks to be selected and erased simultaneously should be 1, 2, 4, 8, 16, 32, 64, or 128, depending on which satisfies all of the following conditions. [condition 1] (number of blocks to be erased) (number of blocks to be selected and erased simultaneously) [condition 2] (start block number) (number of blocks to be selected and erased simultaneously) = remainder is 0 [condition 3] the maximum value among the values that satisfy both conditions 1 and 2 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 168 (2) calculation of the execution count (m) of simultaneous selection and erasure calculation of the executi on count (m) is illustrated in the following flowchart. start er_bknum end_bkno ? st_bkno + 1 sser_bknum 128 note m 0 er_bknum sser_bknum? m m + 1 er_bknum er_ bknum ? sser_bknum sser_bknum sser_bknum 2 note [condition 1] [condition 2] yes yes no no st_bkno: start block number end_bkno: end block number er_bknum: number of blocks to be erased sser_bknum: number of bl ocks to be selected and erased simultaneously m: execution count of simultaneous selection and erasure st_bkno st_bkno + sser_bknum er_ bknum = 0? end yes no st_bkno sser_bknum = remainder is 0? note based on the maximum value of sser_bknum (128), obtai n the value that satisfies conditions 1 and 2 by executing sser_bknum 2; condition 3 is then satisfied. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 169 example 1 erasing blocks 1 to 127 (n (number of blocks to be erased) = 127) <1> the first start block number is 1 and the number of blocks to be erased is 127; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the value that satisfies condition 2 is 1 and the value that satisfies condition 3 is 1, so the number of blocks to be selected and eras ed simultaneously is 1; only block 1 is then erased. <2> after block 1 is erased, the next start blo ck number is 2 and the number of blocks to be erased is 126; the values that satisfy condition 1 ar e therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 ar e 1 and 2, the value that satisfies condition 3 is 2, so the number of blocks to be selected and erased simultaneously is 2; blocks 2 and 3 are then erased. <3> after blocks 2 and 3 are erased, the next star t block number is 4 and the number of blocks to be erased is 124; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 are 1, 2, and 4, the value t hat satisfies condition 3 is 4, so the number of blocks to be selected and erased simultaneously is 4; blocks 4 to 7 are then erased. <4> after blocks 4 to 7 are erased, the next star t block number is 8 and the number of blocks to be erased is 120; the values that sa tisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 are 1, 2, 4, and 8, t he value that satisfies condition 3 is 8, so the number of blocks to be selected and erased simultaneously is 8; blocks 8 to 15 are then erased. <5> after blocks 8 to 15 are erased, the next star t block number is 16 and the number of blocks to be erased is 112; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 ar e 1, 2, 4, 8, and 16, t he value that satisfies condition 3 is 16, so the number of blocks to be selected and erased simultaneously is 16; blocks 16 to 31 are then erased. after blocks 16 to 31 are erased, the next star t block number is 32 and the number of blocks to be erased is 96; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 are 1, 2, 4, 8, 16, and 32, the value that satisfies condition 3 is 32, so the number of blocks to be selected and erased simultaneously is 32; blocks 32 to 63 are then erased. <6> after blocks 32 to 63 are erased, the next star t block number is 64 and the number of blocks to be erased is 64; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, 32, and 64. moreover, the values that satisfy condition 2 ar e 1, 2, 4, 8, 16, 32, and 64, the value that satisfies condition 3 is 64, so the number of blocks to be selected and erased simultaneously is 64; blocks 64 to 127 are then erased. therefore, simultaneous sele ction and erasure is executed seven time s (1, 2 and 3, 4 to 7, 8 to 15, 16 to 31, 32 to 63, and 64 to 127) to erase blocks 1 to 127, so m = 7 is obtained. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 170 block configuration when executi ng simultaneous selection and erasure (when erasing blocks 1 to 127) 128 kb chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 171 example 2 erasing blocks 5 to 10 (n (number of blocks to be erased) = 6) <1> the first start block number is 5 and the number of blocks to be erased is 6; the values that satisfy condition 1 are ther efore 1, 2, and 4. moreover, the value that satisfies condition 2 is 1 and the value that satisfies condition 3 is 1, so the number of blocks to be selected and eras ed simultaneously is 1; only block 5 is the erased. <2> after block 5 is erased, the next start blo ck number is 6 and the number of blocks to be erased is 5; the values that satisfy condi tion 1 are therefore 1, 2, and 4. moreover, the values that satisfy condition 2 ar e 1 and 2, the value that satisfies condition 3 is 2, so the number of blocks to be selected and erased simultaneously is 2; blocks 6 and 7 are then erased. <3> after blocks 6 and 7 are erased, the next star t block number is 8 and the number of blocks to be erased is 3; the values that satisf y condition 1 are therefore 1 and 2. moreover, the values that satisfy condition 2 ar e 1 and 2, the value that satisfies condition 3 is 2, so the number of blocks to be selected and erased simultaneously is 2; blocks 8 and 9 are then erased. <4> after blocks 8 and 9 are erased, the next star t block number is 10 and the number of blocks to be erased is 1; the value that sati sfies condition 1 is therefore 1. this also satisfies conditions 2 and 3, so the number of blocks to be select ed and erased simultaneously is 1; block 10 is then erased. therefore, simultaneous se lection and erasure is ex ecuted four times (5, 6 and 7, 8 and 9, and 10) to erase blocks 5 to 10, so m = 4 is obtained. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 172 block configuration when executi ng simultaneous selection and erasure (when erasing blocks 5 to 10) chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 173 example 3 erasing blocks 25 to 73 (n (number of blocks to be erased) = 49) <1> the first start block number is 25 and the number of blocks to be erased is 49; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, and 32. moreover, the value that satisfies condition 2 is 1 and the value that satisfies condition 3 is 1, so the number of blocks to be selected and eras ed simultaneously is 1; only block 25 is then erased. <2> after block 25 is erased, the next start bl ock number is 26 and the number of blocks to be erased is 48; the values that satisfy condition 1 are therefore 1, 2, 4, 8, 16, and 32. moreover, the values that satisfy condition 2 ar e 1 and 2, the value that satisfies condition 3 is 2, so the number of blocks to be selected and erased simultaneously is 2; blocks 26 and 27 are then erased. <3> after blocks 26 and 27 are erased, the next st art block number is 28 and the number of blocks to be erased is 46; the values that satisfy condi tion 1 are therefore 1, 2, 4, 8, 16, and 32. moreover, the values that satisfy condition 2 are 1, 2, and 4, the value t hat satisfies condition 3 is 4, so the number of blocks to be selected and erased simultaneously is 4; blocks 28 to 31 are then erased. <4> after blocks 28 to 31 are erased, the next star t block number is 32 and the number of blocks to be erased is 42; the values that satisfy conditi on 1 are therefore 1, 2, 4, 8, 16, and 32. moreover, the values that satisfy condition 2 ar e 1, 2, 4, 8, and 32, t he value that satisfies condition 3 is 32, so the number of blocks to be selected and erased simultaneously is 32; blocks 32 to 63 are then erased. <5> after blocks 32 to 63 are erased, the next star t block number is 64, and the number of blocks to be erased is 10; the values that satisfy c ondition 1 are therefore 1, 2, 4, and 8. moreover, the values that satisfy condition 2 are 1, 2, 4, and 8, t he value that satisfies condition 3 is 8, so the number of blocks to be selected and erased simultaneously is 8; blocks 64 to 71 are then erased. <6> after blocks 64 to 71 are erased, the next star t block number is 72, and the number of blocks to be erased is 2; the values that satisf y condition 1 are therefore 1 and 2. moreover, the values that satisfy condition 2 ar e 1 and 2, the value that satisfies condition 3 is 2, so the number of blocks to be selected and erased simultaneously is 2; blocks 72 and 73 are then erased. therefore, simultaneous se lection and erasure is executed six ti mes (25, 26 and 27, 28 to 31, 32 to 63, 64 to 71, and 72 and 73) to erase blocks 25 to 73, so m = 6 is obtained. chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 174 block configuration when executi ng simultaneous selection and erasure (when erasing blocks 25 to 73) chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 175 6.4 uart communication mode (a) data frame txd(output) rxd(input) t dt t dr (b) programming mode setting (at the time of power-on) v dd reset(input) flmd0(input) t dp t pr t rpe t rp t pw t pw t r t f continue into the reset command 0 or 3 pulses (c) programming mode setting (after power-on) v dd reset(input) flmd0(input) t pr t rpe t rp t pw t pw t r t f 0 or 3 pulses t rst "h" continue into the reset command (d) reset command reset(input) t l1 t l2 t 12 t 2c t r1 t wt0 command frame (reset command) status frame txd(output) rxd(input) 00h@9600 bps hi-z remark t x d: t x d6 r x d: r x d6 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 176 (e) chip erase command/block erase command/ bl ock blank check command/oscillating frequency set command t wt1, t wt2, t wt8, t wt9 command frame status frame txd(output) rxd(input) (f) silicon signature command/version get command t wt11, t wt12 status frame command frame data frame t fd2 txd(output) rxd(input) (g) checksum command t wt16 status frame command frame data frame t fd1 txd(output) rxd(input) (h) programming command t wt3 status frame command frame data frame(1) t fd3 status frame(1) t wt4 t fd3 data frame(n) status frame(n-1) status frame(n) t wt4 status frame t wt5 txd(output) rxd(input) txd(output) rxd(input) remark t x d: t x d6 r x d: r x d6 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 177 (i) verify command t wt6 status frame command frame data frame(1) t fd3 status frame(1) t wt7 t wt7 status frame(n-1) data frame(n-1) data frame(n) t fd3 status frame(n) t wt7 txd(output) rxd(input) txd(output) rxd(input) (j) security set command t wt13 status frame command frame data frame t fd3 status frame t wt14 status frame t wt15 txd(output) rxd(input) (k) wait before command frame transmission status frame command frame t com txd(output) rxd(input) remark t x d: t x d6 r x d: r x d6 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 178 6.5 3-wire serial i/o communication mode (a) data frame t dr t dt sck(input) si(input) hi-z hi-z hi-z so(output) (b) programming mode setting (at the time of power-on) v dd reset(input) flmd0(input) t dp t pr t rpe t rp t pw t pw t r t f 8 pulses continue into the reset command (c) programming mode setting (after power-on) v dd reset(input) flmd0(input) t pr t rpe t rp t pw t pw t r t f 8 pulses t rst "h" continue into the reset command (d) reset command reset(input) sck(input) so(output) si(input) t rc t wt0 command frame (reset command) status command status command t sf hi-z hi-z remark sck: sck10 sc: so10 si: si10 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 179 (e) chip erase command/block erase command/block blank check command/oscillating frequency set command t sf t wt1, t wt2, t wt8, t wt9 command frame status command status frame sck(input) so(output) si(input) (f) silicon signature command/version get command t fd2 t wt11, t wt12 status command command frame status frame data frame t sf sck(input) so(output) si(input) (g) checksum command t fd1 t wt16 status command command frame status frame data frame t sf sck(input) so(output) si(input) (h) programming command t wt3 status frame data frame(1) status command command frame status command(1) status frame(1) t sf t fd3 t wt4 t sf t fd3 status command(n) data frame(n) data frame(n) status frame(n-1) status command status frame t wt4 t sf t wt5 t sf sck(input) so(output) si(input) sck(input) so(output) si(input) remark sck: sck10 sc: so10 si: si10 chapter 6 flash memory programming parameter characteristics application note u17739ej3v0an 180 (i) verify command t wt6 t sf t fd3 t wt7 t sf t wt7 status frame(n-1) data frame(n) status command(n-1) data frame(n-1) status command(n) status frame(n) t sf t fd3 t wt7 t sf sck(input) so(output) si(input) sck(input) so(output) si(input) status frame data frame(1) status command command frame status command(1) status frame(1) (j) security set command t wt13 t sf t fd3 t wt14 t sf t wt15 t sf status frame data frame status command command frame status command status frame status command status frame sck(input) so(output) si(input) (k) wait before command frame transmission t com status command status frame command frame t sf sck(input) so(output) si(input) remark sck: sck10 sc: so10 si: si10 application note u17739ej3v0an 181 appendix a circuit diagrams (reference) figure a-1 to a-3 show circuit diagrams of t he programmer and the 78k0/kx2, for reference. appendix a circuit diagram (reference) application note u17739ej3v0an 182 [memo] appendix a circuit diagrams (reference) application note u17739ej3v0an 183 figure a-1. reference circuit diagra m of programmer and 78k0/kx2 (during uart communication: with x1 clock used) appendix a circuit diagrams (reference) application note u17739ej3v0an 185 figure a-2. reference circuit diagram of programmer and 78k0/kx2 (during uart co mmunication: with external clock used) appendix a circuit diagrams (reference) application note u17739ej3v0an 187 figure a-3. reference circuit diagram of pr ogrammer and 78k0/kx2 (during csi communication) application note u17739ej3v0an 189 appendix b revision history b.1 major revisions in this edition page description addition of expanded spec ification products pd78f0500a, 78f0501a, 78f0502a, 78f0503a, 78f0503da, 78f0511a, 78f0512a, 78f0513a, 78f0514a, 78f0515a, 78f0513da, 78f0515da, 78f 0521a, 78f0522a, 78f0523a, 78f0524a, 78F0525a, 78f0526a,78f0527a, 78f0527da, 78f0531a, 78f 0532a, 78f0533a, 78f0534a, 78f0535a, 78f0536a, 78f0537a, 78f0537da, 78f0544a, 78f0545a, 78f0546a, 78f0547a, 78f0547da deletion of 2.1 programmer control pins and 2.2 details of control pins throughout move of 9 sections (from 2.3 basic flowchart to 2.11 status list ) to chapter 1 flash memory programming p.32 modification of description in 3.5 chip erase command p.39 modification of table 3-1. example of silicon signature data (in case of pd78f0522 (78k0/kd2)) pp.41 to 45 modification of 3.10.4 78k0/kx2 silicon signature list pp.52 to 54 from 4.1 command frame transmission processing flowchart to 4.3 data frame reception processing flowchart ? modification of the symbol in the flowchart pp.104 to 106 from 5.1 command frame transmission processing flowchart to 5.3 data frame reception processing flowchart ? modification of the symbol in the flowchart p.108 modification of 5.4.3 status at processing completion pp.161 to 164 addition of 6.1 flash memory programming parameter characteristics of expanded specification products ( pd78f05xxa) p.164 modification of 6.2.2 flash memory programming mode setting time pp.165 to 167 modification of 6.2.3 programming characteristics p.175 addition of 6.4 (c) programming mode setting (after power-on) p.178 modification of 6.5 3-wire serial i/o communication mode p.190 addition of b.2 revision history up to previous edition application note u17739ej3v0an 190 b.2 revision history up to previous edition the following table shows the revision hi story up to the previous editions. the ?applied to:? column indicates the chapters of each edition in wh ich the revision was applied. (1/2) edition major revision from pr evious edition applied to: modification of figure 2-5. basic flowchart for flash memory rewrite processing addition of 2.4.1 mode setting flowchart addition of 2.4.2 sample program chapter 2 programmer operating environment 6.8.3 status at processing completion ? deletion of flmd error in abnormal termination [d] 6.9.3 status at processing completion ? deletion of description of parameter error in abnormal termination [b] 6.11.3 status at processing completion ? addition of read error in abnormal termination [b] modification of 6.14.5 sample program chapter 6 uart communication mode addition of note in 7.4.1 processing sequence chart modification of description and addition of note in 7.4.2 description of processing sequence addition of note in 7.4.4 flowchart modification of 7.4.5 sample program modification of 7.5.5 sample program modification of 7.6.5 sample program modification of 7.7.5 sample program modification of 7.8.5 sample program 7.9.3 status at processing completion ? deletion of flmd error in abnormal termination [d] modification of 7.9.5 sample program modification of 7.10.5 sample program modification of 7.11.5 sample program 7.12.3 status at processing completion ? addition of read error in abnormal termination [b] modification of 7.12.5 sample program modification of 7.13.5 sample program modification of 7.14.5 sample program modification of 7.15.5 sample program chapter 7 3-wire serial i/o communication mode (csi) modification of wait for low-level data 1 (uart) in 8.2 flash memory programming mode setting time chapter 8 flash memory programming parameter characteristics 2nd edition deletion of chapter 9 electrical specifications (reference) previous edition chapter 9 electrical specifications (reference) appendix e revision history user?s manual u17739ej3v0an 191 (2/2) edition major revision from pr evious edition applied to: modification of figure a-1. reference circuit diagram of programmer and 78k0/kx2 (during uart communication: with x1 clock used) to figure a-3. reference circuit diagram of programmer and 78k0/kx2 (during csi communication) appendix a circuit diagrams (reference) 2nd edition addition of appendix b revision history appendix b revision history nec electronics corporation 1753, shimon u ma b e, n akahara-k u , ka w asaki, kanaga w a 211- 8 66 8 , japan tel: 044-435-5111 http:// www .necel.com/ [america] nec electronics america, inc. 2 88 0 scott bl v d. santa clara, ca 95050-2554, u.s.a. tel: 40 8 -5 88 -6000 8 00-366-97 8 2 http:// www .am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, q u ant u m plaza, n o. 27 zhich u nl u haidian district, beijing 1000 8 3, p.r.china tel: 010- 8 235-1155 http:// www .cn.necel.com/ shan g hai branch room 2509-2510, bank of china to w er, 200 yincheng road central, p u dong n e w area, shanghai, p.r.china p.c:200120 tel:021-5 888 -5400 http:// www .cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times sq u are b u ilding, n o. 406 8 yi tian road, f u tian district, shenzhen, p.r.china p.c:51 8 04 8 tel:0755- 8 2 8 2-9 8 00 http:// www .cn.necel.com/ nec electronics hon g kon g ltd. unit 1601-1613, 16/f., to w er 2, grand cent u ry place, 193 prince ed w ard road w est, mongkok, ko w loon, hong kong tel: 2 88 6-931 8 http:// www .hk.necel.com/ nec electronics taiwan ltd. 7f, n o. 363 f u shing n orth road taipei, tai w an, r. o. c. tel: 02- 8 175-9600 http:// www .t w .necel.com/ nec electronics sin g apore pte. ltd. 23 8 a thomson road, #12-0 8 n o v ena sq u are, singapore 3076 8 4 tel: 6253- 8 311 http:// www .sg.necel.com/ nec electronics korea ltd. 11f., samik la v ied?or bldg., 720-2, yeoksam-dong, kangnam-k u , seo u l, 135-0 8 0, korea tel: 02-55 8 -3737 http:// www .kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http:// www .e u .necel.com/ hanover office pod b ielskistrasse 166 b 30177 hanno v er tel: 0 511 33 40 2-0 munich office w erner-eckert-strasse 9 8 1 8 29 mnchen tel: 0 8 9 92 10 03-0 stutt g art office ind u striestrasse 3 70565 st u ttgart tel: 0 711 99 01 0-0 united kin g dom branch cygn u s ho u se, s u nrise park w ay linford w ood, milton keynes mk14 6 n p, u.k. tel: 0190 8 -691-133 succursale fran?aise 9, r u e pa u l da u tier, b.p. 52 7 8 142 v elizy- v illaco ub lay cdex france tel: 01-3067-5 8 00 sucursal en espa?a j u an esplandi u , 15 2 8 007 madrid, spain tel: 091-504-27 8 7 tyskland filial t? b y centr u m entrance s (7th floor) 1 8 322 t? b y, s w eden tel: 0 8 63 8 72 00 filiale italiana v ia fa b io filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijger w eg 6 5616 hs eindho v en the n etherlands tel: 040 265 40 10 |
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